clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks

Early revisions of the R-Car V4M Series Hardware User’s Manual
contained an incorrect formula for the CPU core clocks:

    ZCnφ = (PLL2VCO x 1/2) x mult/32

Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the
parent clock.

In Rev.0.70 of the documentation, the formula was corrected to:

    ZCnφ = (PLL2VCO x 1/4) x mult/32

As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2,
the use of CLK_PLL2_DIV2 is a recurring source of confusion.  Hence get
rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the
invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4
(and Gen3) SoCs.

Reported-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/0d2789cac2bf306145fe0bbf269c2da5942bb68f.1728377724.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
index e20c048bfa9be1429c600aa1513216dd3847812a..9067e407cbc69f0037efb86c5bb06e68db80a9ee 100644 (file)
--- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
@@ -37,7 +37,6 @@ enum clk_ids {
        CLK_PLL5,
        CLK_PLL6,
        CLK_PLL1_DIV2,
-       CLK_PLL2_DIV2,
        CLK_PLL3_DIV2,
        CLK_PLL4_DIV2,
        CLK_PLL4_DIV5,
@@ -78,7 +77,6 @@ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = {
        DEF_GEN4_PLL_V8_25(".pll6", 6,  CLK_PLL6,               CLK_MAIN),
 
        DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,  CLK_PLL1,       2, 1),
-       DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2,  CLK_PLL2,       2, 1),
        DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2,  CLK_PLL3,       2, 1),
        DEF_FIXED(".pll4_div2", CLK_PLL4_DIV2,  CLK_PLL4,       2, 1),
        DEF_FIXED(".pll4_div5", CLK_PLL4_DIV5,  CLK_PLL4,       5, 1),
@@ -101,10 +99,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = {
        DEF_RATE(".oco",        CLK_OCO,        32768),
 
        /* Core Clock Outputs */
-       DEF_GEN4_Z("zc0",       R8A779H0_CLK_ZC0,       CLK_TYPE_GEN4_Z,        CLK_PLL2_DIV2,  2, 0),
-       DEF_GEN4_Z("zc1",       R8A779H0_CLK_ZC1,       CLK_TYPE_GEN4_Z,        CLK_PLL2_DIV2,  2, 8),
-       DEF_GEN4_Z("zc2",       R8A779H0_CLK_ZC2,       CLK_TYPE_GEN4_Z,        CLK_PLL2_DIV2,  2, 32),
-       DEF_GEN4_Z("zc3",       R8A779H0_CLK_ZC3,       CLK_TYPE_GEN4_Z,        CLK_PLL2_DIV2,  2, 40),
+       DEF_GEN4_Z("zc0",       R8A779H0_CLK_ZC0,       CLK_TYPE_GEN4_Z,        CLK_PLL2,       4, 0),
+       DEF_GEN4_Z("zc1",       R8A779H0_CLK_ZC1,       CLK_TYPE_GEN4_Z,        CLK_PLL2,       4, 8),
+       DEF_GEN4_Z("zc2",       R8A779H0_CLK_ZC2,       CLK_TYPE_GEN4_Z,        CLK_PLL2,       4, 32),
+       DEF_GEN4_Z("zc3",       R8A779H0_CLK_ZC3,       CLK_TYPE_GEN4_Z,        CLK_PLL2,       4, 40),
        DEF_FIXED("s0d2",       R8A779H0_CLK_S0D2,      CLK_S0,         2, 1),
        DEF_FIXED("s0d3",       R8A779H0_CLK_S0D3,      CLK_S0,         3, 1),
        DEF_FIXED("s0d4",       R8A779H0_CLK_S0D4,      CLK_S0,         4, 1),