opcodes/

	* sparc-opc.c (sparc_opcodes): Fix random instruction to write
	to a float instead of an integer register.

gas/testsuite/

	* gas/sparc/hpcvis3.s: Update to use float reg for random insn.
	* gas/sparc/hpcvis3.d: Likewise.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 5def8f523b48fdefc2f0a99ea585f0ee43e9fa14..9df84ae0ad7a8b5af9eed488788f109cc82417ba 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2011-09-27  David S. Miller  <davem@davemloft.net>
+
+       * gas/sparc/hpcvis3.s: Update to use float reg for random insn.
+       * gas/sparc/hpcvis3.d: Likewise.
+
 2011-09-26  David S. Miller  <davem@davemloft.net>
 
        * gas/sparc/ima.d: New test.

diff --git a/gas/testsuite/gas/sparc/hpcvis3.d b/gas/testsuite/gas/sparc/hpcvis3.d
index faa3137c9d2e79c0b6f69ec381e8e45e8bff6268..f4606ac20a05ce622c11830cdd010f4448cab5a8 100644 (file)
--- a/gas/testsuite/gas/sparc/hpcvis3.d
+++ b/gas/testsuite/gas/sparc/hpcvis3.d
@@ -41,7 +41,7 @@ Disassembly of section .text:
   7c:  95 f9 11 c6     fnumaddd  %f4, %f6, %f8, %f10
   80:  8f b1 42 26     addxc  %g5, %g6, %g7
   84:  97 b2 42 6a     addxccc  %o1, %o2, %o3
-  88:  99 b0 02 a0     random  %o4
+  88:  8d b0 02 a0     random  %f6
   8c:  9f b3 42 ce     umulxhi  %o5, %sp, %o7
   90:  b5 b0 02 f9     lzd  %i1, %i2
   94:  81 b0 03 7b     cmask8  %i3

diff --git a/gas/testsuite/gas/sparc/hpcvis3.s b/gas/testsuite/gas/sparc/hpcvis3.s
index 8da08f42180efbe1a28753e3217256437bf2f0bc..9f3ac368ec19b024746d09960a2d87155e7a2a87 100644 (file)
--- a/gas/testsuite/gas/sparc/hpcvis3.s
+++ b/gas/testsuite/gas/sparc/hpcvis3.s
@@ -34,7 +34,7 @@
        fnumaddd %f4, %f6, %f8, %f10
        addxc   %g5, %g6, %g7
        addxccc %o1, %o2, %o3
-       random  %o4
+       random  %f6
        umulxhi %o5, %o6, %o7
        lzd     %i1, %i2
        cmask8  %i3

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 67bfbdfe05109729e8b2c4382a3fd15dbf95e2f4..051f52a475780ac7df902f2525f54102bd4c9929 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2011-09-27  David S. Miller  <davem@davemloft.net>
+
+       * sparc-opc.c (sparc_opcodes): Fix random instruction to write
+       to a float instead of an integer register.
+
 2011-09-26  David S. Miller  <davem@davemloft.net>
 
        * sparc-opc.c (sparc_opcodes): Add integer multiply-add

diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 6fbe0251f201ab90d08b21fafb7a0007122dff63..a2096c5a90b9165431539c142571c3e3a6d2d34a 100644 (file)
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -1869,7 +1869,7 @@ SLCBCC("cbnefr", 15),
 { "fnumaddd",  F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT|F_FJFMAU, v9b },
 { "addxc",     F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", F_VIS3, v9b },
 { "addxccc",   F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", F_VIS3, v9b },
-{ "random",    F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "d", F_RANDOM, v9b },
+{ "random",    F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "H", F_FLOAT|F_RANDOM, v9b },
 { "umulxhi",   F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", F_VIS3, v9b },
 { "lzd",       F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_VIS3, v9b },
 { "cmask8",    F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", F_VIS3, v9b },