RISC-V: Add patterns for vector-scalar multiply-(subtract-)accumulate [PR119100]

This pattern enables the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into a plus-mult or minus-mult RTL instruction.

Before this patch, we have two instructions, e.g.:
  vfmv.v.f       v6,fa0
  vfmacc.vv      v2,v6,v4

After, we get only one:
  vfmacc.vf      v2,fa0,v4

	PR target/119100

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*<optab>_vf_<mode>): Handle both add and
	acc FMA variants.
	* config/riscv/vector.md (*pred_mul_<optab><mode>_scalar_undef): New.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfmacc and vfmsac.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h: Add support for acc
	variants.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c: Define
	TEST_OUT.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c: New test.

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index e8293135af32e393f5cf6ba45549822c593e8e60..bb15d14b4e64396dd9b11997767e8bd69aabd8ba 100644 (file)
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1721,24 +1721,26 @@
 ;; - vfmsub.vf
 ;; - vfnmadd.vf
 ;; - vfnmsub.vf
+;; - vfmacc.vf
+;; - vfmsac.vf
 ;; =============================================================================
 
-;; vfmadd.vf, vfmsub.vf
+;; vfmadd.vf, vfmsub.vf, vfmacc.vf, vfmsac.vf
 (define_insn_and_split "*<optab>_vf_<mode>"
-  [(set (match_operand:V_VLSF 0 "register_operand"             "=vd")
+  [(set (match_operand:V_VLSF 0 "register_operand")
     (plus_minus:V_VLSF
            (mult:V_VLSF
              (vec_duplicate:V_VLSF
-               (match_operand:<VEL> 1 "register_operand"       "  f"))
-             (match_operand:V_VLSF 2 "register_operand"        "  0"))
-           (match_operand:V_VLSF 3 "register_operand"          " vr")))]
+               (match_operand:<VEL> 1 "register_operand"))
+             (match_operand:V_VLSF 2 "register_operand"))
+           (match_operand:V_VLSF 3 "register_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
   [(const_int 0)]
   {
     rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
-                operands[2]};
+                RVV_VUNDEF(<MODE>mode)};
     riscv_vector::emit_vlmax_insn (code_for_pred_mul_scalar (<CODE>, <MODE>mode),
                                   riscv_vector::TERNARY_OP_FRM_DYN, ops);
     DONE;

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 851ba4a9490a8d613ab2bb836bb4026ca7e3f1e2..aaea115339381197ac28a2a235efb8664e90b4bd 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6599,9 +6599,42 @@
                (match_operand:<VEL> 2 "register_operand"))
              (match_operand:V_VLSF 3 "register_operand"))
            (match_operand:V_VLSF 4 "register_operand"))
-         (match_operand:V_VLSF 5 "register_operand")))]
+         (match_operand:V_VLSF 5 "vector_merge_operand")))]
   "TARGET_VECTOR"
-{})
+{
+  riscv_vector::prepare_ternary_operands (operands);
+})
+
+(define_insn "*pred_mul_<optab><mode>_scalar_undef"
+  [(set (match_operand:V_VLSF 0 "register_operand"           "=vd,vd, vr, vr")
+       (if_then_else:V_VLSF
+         (unspec:<VM>
+           [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
+            (match_operand 6 "vector_length_operand"    "rvl,rvl,rvl,rvl")
+            (match_operand 7 "const_int_operand"        "  i,  i,  i,  i")
+            (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
+            (match_operand 9 "const_int_operand"        "  i,  i,  i,  i")
+            (match_operand 10 "const_int_operand"       "  i,  i,  i,  i")
+            (reg:SI VL_REGNUM)
+            (reg:SI VTYPE_REGNUM)
+            (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+         (plus_minus:V_VLSF
+           (mult:V_VLSF
+             (vec_duplicate:V_VLSF
+               (match_operand:<VEL> 3 "register_operand"    "  f,  f,  f,  f"))
+             (match_operand:V_VLSF 4 "register_operand"     "  0, vr,  0, vr"))
+           (match_operand:V_VLSF 5 "register_operand"       " vr,  0, vr,  0"))
+         (match_operand:V_VLSF 2 "vector_undef_operand")))]
+  "TARGET_VECTOR"
+  "@
+   vf<madd_msub>.vf\t%0,%3,%5%p1
+   vf<macc_msac>.vf\t%0,%3,%4%p1
+   vf<madd_msub>.vf\t%0,%3,%5%p1
+   vf<macc_msac>.vf\t%0,%3,%4%p1"
+  [(set_attr "type" "vfmuladd")
+   (set_attr "mode" "<MODE>")
+   (set (attr "frm_mode")
+       (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
 
 (define_insn "*pred_<madd_msub><mode>_scalar"
   [(set (match_operand:V_VLSF 0 "register_operand"            "=vd, vr")

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
index 09f4b71f30db864c4544aa5a65ca4bd8808ddf1d..10ee2d82597ffa0a75764e4fc56cb5f8b3a78017 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
@@ -7,8 +7,12 @@ DEF_VF_MULOP_CASE_0 (_Float16, +, +, add)
 DEF_VF_MULOP_CASE_0 (_Float16, -, +, sub)
 DEF_VF_MULOP_CASE_0 (_Float16, +, -, nadd)
 DEF_VF_MULOP_CASE_0 (_Float16, -, -, nsub)
+DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, +, acc)
+DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, +, sac)
 
 /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfnmadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
index b21ae49bd5fd02700a9132c2a0a094aa5b816251..3492c7f1ff8246e45876eb7606a1ff883765ff26 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
@@ -7,8 +7,12 @@ DEF_VF_MULOP_CASE_0 (float, +, +, add)
 DEF_VF_MULOP_CASE_0 (float, -, +, sub)
 DEF_VF_MULOP_CASE_0 (float, +, -, nadd)
 DEF_VF_MULOP_CASE_0 (float, -, -, nsub)
+DEF_VF_MULOP_ACC_CASE_0 (float, +, +, acc)
+DEF_VF_MULOP_ACC_CASE_0 (float, -, +, sac)
 
 /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfnmadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
index 56a44dd065def17493f2c1dd42fdae1a2917d296..3ee2fbb9cd5d277dc39a41fca708d0b2f2d251b5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
@@ -7,8 +7,12 @@ DEF_VF_MULOP_CASE_0 (double, +, +, add)
 DEF_VF_MULOP_CASE_0 (double, -, +, sub)
 DEF_VF_MULOP_CASE_0 (double, +, -, nadd)
 DEF_VF_MULOP_CASE_0 (double, -, -, nsub)
+DEF_VF_MULOP_ACC_CASE_0 (double, +, +, acc)
+DEF_VF_MULOP_ACC_CASE_0 (double, -, +, sac)
 
 /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfnmadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
index 22180cb53cd1a0590f576e6fb9287eb2ac4b51eb..1e4b8064228b67adf44b520eea88035abff89f6b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
@@ -1,14 +1,11 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=1" } */
 
-#include "vf_mulop.h"
-
-DEF_VF_MULOP_CASE_0 (_Float16, +, +, add)
-DEF_VF_MULOP_CASE_0 (_Float16, -, +, sub)
-DEF_VF_MULOP_CASE_0 (_Float16, +, -, nadd)
-DEF_VF_MULOP_CASE_0 (_Float16, -, -, nsub)
+#include "vf-1-f16.c"
 
 /* { dg-final { scan-assembler-not {vfmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
+/* { dg-final { scan-assembler-not {vfmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
index 318c281d0c10d3f5fde43c8175e388b96a79bced..48d87c4a690bd4b70fbce14e57d4d6c60bab495d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
@@ -1,14 +1,11 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=1" } */
 
-#include "vf_mulop.h"
-
-DEF_VF_MULOP_CASE_0 (float, +, +, add)
-DEF_VF_MULOP_CASE_0 (float, -, +, sub)
-DEF_VF_MULOP_CASE_0 (float, +, -, nadd)
-DEF_VF_MULOP_CASE_0 (float, -, -, nsub)
+#include "vf-1-f32.c"
 
 /* { dg-final { scan-assembler-not {vfmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
+/* { dg-final { scan-assembler-not {vfmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
index 318c281d0c10d3f5fde43c8175e388b96a79bced..ad7beab26241b97e674e49097af738f461ec64dc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
@@ -1,14 +1,11 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=1" } */
 
-#include "vf_mulop.h"
-
-DEF_VF_MULOP_CASE_0 (float, +, +, add)
-DEF_VF_MULOP_CASE_0 (float, -, +, sub)
-DEF_VF_MULOP_CASE_0 (float, +, -, nadd)
-DEF_VF_MULOP_CASE_0 (float, -, -, nsub)
+#include "vf-1-f64.c"
 
 /* { dg-final { scan-assembler-not {vfmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
+/* { dg-final { scan-assembler-not {vfmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
index 382f7ef50a9c94cdf663003cb4c9793600a07b17..47f7cd1790c8fa57683ed27a8e73c67b68d0dd4e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
@@ -7,8 +7,12 @@ DEF_VF_MULOP_CASE_1 (_Float16, +, +, add, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (_Float16, -, +, sub, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (_Float16, +, -, nadd, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (_Float16, -, -, nsub, VF_MULOP_BODY_X16)
+DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, +, acc, VF_MULOP_ACC_BODY_X128)
+DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, +, sac, VF_MULOP_ACC_BODY_X128)
 
 /* { dg-final { scan-assembler {vfmadd.vf} } } */
 /* { dg-final { scan-assembler {vfmsub.vf} } } */
 /* { dg-final { scan-assembler {vfnmadd.vf} } } */
 /* { dg-final { scan-assembler {vfnmsub.vf} } } */
+/* { dg-final { scan-assembler {vfmacc.vf} } } */
+/* { dg-final { scan-assembler {vfmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
index db2cd2eaabfbd67d77eec50481fc1a45d108686a..5877dec8b189c131e1a0a69e682739b97a56c778 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
@@ -7,8 +7,12 @@ DEF_VF_MULOP_CASE_1 (float, +, +, add, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (float, -, +, sub, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (float, +, -, nadd, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (float, -, -, nsub, VF_MULOP_BODY_X16)
+DEF_VF_MULOP_ACC_CASE_1 (float, +, +, acc, VF_MULOP_ACC_BODY_X128)
+DEF_VF_MULOP_ACC_CASE_1 (float, -, +, sac, VF_MULOP_ACC_BODY_X128)
 
 /* { dg-final { scan-assembler {vfmadd.vf} } } */
 /* { dg-final { scan-assembler {vfmsub.vf} } } */
 /* { dg-final { scan-assembler {vfnmadd.vf} } } */
 /* { dg-final { scan-assembler {vfnmsub.vf} } } */
+/* { dg-final { scan-assembler {vfmacc.vf} } } */
+/* { dg-final { scan-assembler {vfmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
index 423b4db396683a1ced9b6a2708ac441fcaf8cb46..7073502e00ee5bd58bf4a92ec57b076c7e570181 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
@@ -7,8 +7,12 @@ DEF_VF_MULOP_CASE_1 (double, +, +, add, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (double, -, +, sub, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (double, +, -, nadd, VF_MULOP_BODY_X16)
 DEF_VF_MULOP_CASE_1 (double, -, -, nsub, VF_MULOP_BODY_X16)
+DEF_VF_MULOP_ACC_CASE_1 (double, +, +, acc, VF_MULOP_ACC_BODY_X128)
+DEF_VF_MULOP_ACC_CASE_1 (double, -, +, sac, VF_MULOP_ACC_BODY_X128)
 
 /* { dg-final { scan-assembler {vfmadd.vf} } } */
 /* { dg-final { scan-assembler {vfmsub.vf} } } */
 /* { dg-final { scan-assembler {vfnmadd.vf} } } */
 /* { dg-final { scan-assembler {vfnmsub.vf} } } */
+/* { dg-final { scan-assembler {vfmacc.vf} } } */
+/* { dg-final { scan-assembler {vfmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
index 1482ff0fdf8edc9e15ce8d366538c9b0e6b65a86..dc7f252ce37f34939cc2f1d0f8bd5ad816025fd2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
@@ -1,14 +1,11 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=4" } */
 
-#include "vf_mulop.h"
-
-DEF_VF_MULOP_CASE_1 (_Float16, +, +, add, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (_Float16, -, +, sub, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (_Float16, +, -, nadd, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (_Float16, -, -, nsub, VF_MULOP_BODY_X16)
+#include "vf-3-f16.c"
 
 /* { dg-final { scan-assembler-not {vfmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
+/* { dg-final { scan-assembler-not {vfmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
index d1368e773d85cd933606c387b4facf203c472676..c62711fb40fb2baa6a5800aa960fa3cd429eb44f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
@@ -1,14 +1,11 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */
 
-#include "vf_mulop.h"
-
-DEF_VF_MULOP_CASE_1 (float, +, +, add, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (float, -, +, sub, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (float, +, -, nadd, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (float, -, -, nsub, VF_MULOP_BODY_X16)
+#include "vf-3-f32.c"
 
 /* { dg-final { scan-assembler-not {vfmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
+/* { dg-final { scan-assembler-not {vfmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
index 8e4bdd4b15a2cb001f1900dd815c197dbec27ac7..d0c82cf41f2121779d68aee7a4f61ef8a76a765c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
@@ -1,14 +1,11 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */
 
-#include "vf_mulop.h"
-
-DEF_VF_MULOP_CASE_1 (double, +, +, add, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (double, -, +, sub, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (double, +, -, nadd, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (double, -, -, nsub, VF_MULOP_BODY_X16)
+#include "vf-3-f64.c"
 
 /* { dg-final { scan-assembler-not {vfmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfmsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfnmsub.vf} } } */
+/* { dg-final { scan-assembler-not {vfmacc.vf} } } */
+/* { dg-final { scan-assembler-not {vfmsac.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h
index 433a16e4eecf06efb0e30c640daecd09c745a5ee..98fa8fa42df2153e540f136fc6a0e2d38a4eccd9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h
@@ -17,6 +17,23 @@
 #define RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)                       \
   RUN_VF_MULOP_CASE_0(T, NAME, out, in, x, n)
 
+#define DEF_VF_MULOP_ACC_CASE_0(T, OP, NEG, NAME)                              \
+  T test_vf_mulop_acc_##NAME##_##T##_case_0 (T *restrict out, T *restrict in,  \
+                                            T f, unsigned n)                  \
+  {                                                                            \
+    unsigned i;                                                                \
+    for (i = 0; i < n; i++)                                                    \
+      out[i] = NEG (f * in[i] OP out[i]);                                      \
+    /* Ensure that we get acc rather than add by reusing the multiplicand. */  \
+    return in[i - 1];                                                          \
+  }
+#define DEF_VF_MULOP_ACC_CASE_0_WRAP(T, OP, NEG, NAME)                         \
+  DEF_VF_MULOP_ACC_CASE_0 (T, OP, NEG, NAME)
+#define RUN_VF_MULOP_ACC_CASE_0(T, NAME, out, in, x, n)                        \
+  test_vf_mulop_acc_##NAME##_##T##_case_0 (out, in, x, n)
+#define RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, out, in, x, n)                   \
+  RUN_VF_MULOP_ACC_CASE_0 (T, NAME, out, in, x, n)
+
 #define VF_MULOP_BODY(op, neg)                                                 \
   out[k + 0] = neg (tmp * out[k + 0] op in[k + 0]);                            \
   out[k + 1] = neg (tmp * out[k + 1] op in[k + 1]);                            \
@@ -62,4 +79,53 @@
 #define DEF_VF_MULOP_CASE_1_WRAP(T, OP, NEG, NAME, BODY)                       \
   DEF_VF_MULOP_CASE_1 (T, OP, NEG, NAME, BODY)
 
+#define VF_MULOP_ACC_BODY(op, neg)                                             \
+  out[k + 0] = neg (tmp * in[k + 0] op out[k + 1]);                            \
+  out[k + 1] = neg (tmp * in[k + 1] op out[k + 1]);                            \
+  k += 2;
+
+#define VF_MULOP_ACC_BODY_X4(op, neg)                                          \
+  VF_MULOP_ACC_BODY (op, neg)                                                  \
+  VF_MULOP_ACC_BODY (op, neg)
+
+#define VF_MULOP_ACC_BODY_X8(op, neg)                                          \
+  VF_MULOP_ACC_BODY_X4 (op, neg)                                               \
+  VF_MULOP_ACC_BODY_X4 (op, neg)
+
+#define VF_MULOP_ACC_BODY_X16(op, neg)                                         \
+  VF_MULOP_ACC_BODY_X8 (op, neg)                                               \
+  VF_MULOP_ACC_BODY_X8 (op, neg)
+
+#define VF_MULOP_ACC_BODY_X32(op, neg)                                         \
+  VF_MULOP_ACC_BODY_X16 (op, neg)                                              \
+  VF_MULOP_ACC_BODY_X16 (op, neg)
+
+#define VF_MULOP_ACC_BODY_X64(op, neg)                                         \
+  VF_MULOP_ACC_BODY_X32 (op, neg)                                              \
+  VF_MULOP_ACC_BODY_X32 (op, neg)
+
+#define VF_MULOP_ACC_BODY_X128(op, neg)                                        \
+  VF_MULOP_ACC_BODY_X64 (op, neg)                                              \
+  VF_MULOP_ACC_BODY_X64 (op, neg)
+
+#define VF_MULOP_ACC_BODY_X256(op, neg)                                        \
+  VF_MULOP_ACC_BODY_X128 (op, neg)                                             \
+  VF_MULOP_ACC_BODY_X128 (op, neg)
+
+#define DEF_VF_MULOP_ACC_CASE_1(T, OP, NEG, NAME, BODY)                        \
+  T test_vf_mulop_acc_##NAME##_##T##_case_1 (T *restrict out, T *restrict in,  \
+                                            T x, unsigned n)                  \
+  {                                                                            \
+    unsigned k = 0;                                                            \
+    T tmp = x + 3;                                                             \
+                                                                               \
+    while (k < n)                                                              \
+      {                                                                        \
+       tmp = tmp * 0x3f;                                                      \
+       BODY (OP, NEG)                                                         \
+      }                                                                        \
+  }
+#define DEF_VF_MULOP_ACC_CASE_1_WRAP(T, OP, NEG, NAME, BODY)                   \
+  DEF_VF_MULOP_ACC_CASE_1 (T, OP, NEG, NAME, BODY)
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h
index 579f841e6a733da70b1c8459f4fb7fcb854c7211..3dc39993e74e59d0df060fbe5c6f0a3ce3c2c93e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h
@@ -14,15 +14,15 @@ main ()
   for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++)
     {
       T f = TEST_DATA[i][0][0];
-      T *in = TEST_DATA[i][1];
-      T *out = TEST_DATA[i][2];
+      T *b = TEST_DATA[i][1];
+      T *c = TEST_DATA[i][2];
       T *expect = TEST_DATA[i][3];
 
-      TEST_RUN (T, NAME, out, in, f, N);
+      TEST_RUN (T, NAME, c, b, f, N);
 
       for (k = 0; k < N; k++)
        {
-         T diff = expect[k] - out[k];
+         T diff = expect[k] - TEST_OUT[k];
          if (TYPE_FABS (diff, T) > .01 * TYPE_FABS (expect[k], T))
            __builtin_abort ();
        }

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
new file mode 100644 (file)
index 0000000..5bb926d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    _Float16
+#define NAME add
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, +, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c
new file mode 100644 (file)
index 0000000..357c4ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    float
+#define NAME add
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, +, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c
new file mode 100644 (file)
index 0000000..0da46be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    double
+#define NAME add
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, +, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
index 9ec5303df4f96c90b50a33099e467f148d4f6dea..be4dc1dadd2dd349e6658ea4773212ef43e2e10a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP (T, +, +, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c
index 222efeceb472207e4763df1ba8439a262ea755df..ed9bd36c620e683c891aa643167a66436f56dd83 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP (T, +, +, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c
index 300d5205d79de3e33af2be7062c4e252d2da9833..b0883df36a469158a0f50ad22e29197c2a560981 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP (T, +, +, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
new file mode 100644 (file)
index 0000000..812e608
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    _Float16
+#define NAME sub
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, +, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c
new file mode 100644 (file)
index 0000000..3f03e11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    float
+#define NAME sub
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, +, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c
new file mode 100644 (file)
index 0000000..0df8d3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_mulop.h"
+#include "vf_mulop_data.h"
+
+#define T    double
+#define NAME sub
+
+DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, +, NAME)
+
+#define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n)
+#define TEST_OUT b
+
+#include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
index d11d446f515697f5d650586d1fd18588988732a3..48c288001a180996dd3400c144955d798d975983 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP (T, -, +, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c
index 500e1b25a7368afb95672db32547b7e97a91d28f..d3cd3c19e2afa221e2c4530a930c637153a72f6c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP (T, -, +, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c
index a2c32943ae784b95542056c8a46256c31d524008..0d615da914025ef4266659d1b41b37f7e30b216f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP (T, -, +, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
index a45e1f854fd5c29c6054b37aa48a7085e79f566f..2be891776186b1cac144644894b17ae168d19891 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP(T, +, -, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c
index b8a7bc4fee5cc574a5cfb5cdd8414b923b771e4b..38d4f7da3bc1633f847ccbedd945d7164024c96d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP (T, +, -, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c
index 32664e1fb0e98e1f9e5764d3ab08cdc54c99457f..dc9d3a0560d657c88f12fd07e2442ce160e594ab 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP (T, +, -, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
index a1b0034e620588f91d0c7b54b2dec9dea823b078..7bed0ed940c9b7230096f8541992a594c73c1667 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP (T, -, -, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c
index 6450573484f3e27ad3214dd1425d5e7eadef4c1e..3cbeea9da68691267d8170986c790ebc905f29a4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP (T, -, -, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c
index eb3ca1c6acaef0ce367ff47aaec5e007797bb551..00ead93493c057891d335008e789dceab3dab240 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c
@@ -11,5 +11,6 @@ DEF_VF_MULOP_CASE_0_WRAP (T, -, -, NAME)
 
 #define TEST_DATA                        TEST_MULOP_DATA_WRAP(T, NAME)
 #define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n)
+#define TEST_OUT c
 
 #include "vf_mulop_run.h"