--- /dev/null
+From c154a76311293f9671439286834aa325b7ef59fe Mon Sep 17 00:00:00 2001
+From: Christian König <christian.koenig@amd.com>
+Date: Wed, 30 Oct 2013 12:56:04 +0100
+Subject: drm/radeon: activate UVD clocks before sending the destroy msg
+
+From: Christian König <christian.koenig@amd.com>
+
+commit c154a76311293f9671439286834aa325b7ef59fe upstream.
+
+Make sure the UVD clocks are still active before sending
+the destroy message, otherwise the hw might hang.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_uvd.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/radeon_uvd.c
++++ b/drivers/gpu/drm/radeon/radeon_uvd.c
+@@ -242,6 +242,8 @@ void radeon_uvd_free_handles(struct rade
+ if (handle != 0 && rdev->uvd.filp[i] == filp) {
+ struct radeon_fence *fence;
+
++ radeon_uvd_note_usage(rdev);
++
+ r = radeon_uvd_get_destroy_msg(rdev,
+ R600_RING_TYPE_UVD_INDEX, handle, &fence);
+ if (r) {
--- /dev/null
+From 70471860ff9f335c60c004d42ebd48945bfa5403 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 31 Oct 2013 16:43:27 -0400
+Subject: drm/radeon: don't share PPLLs on DCE4.1
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 70471860ff9f335c60c004d42ebd48945bfa5403 upstream.
+
+Sharing PPLLs seems to cause problems on some boards.
+
+Bug:
+https://bugs.freedesktop.org/show_bug.cgi?id=45334
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atombios_crtc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_crtc.c
++++ b/drivers/gpu/drm/radeon/atombios_crtc.c
+@@ -1683,7 +1683,7 @@ static int radeon_atom_pick_pll(struct d
+ if (pll != ATOM_PPLL_INVALID)
+ return pll;
+ }
+- } else {
++ } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */
+ /* use the same PPLL for all monitors with the same clock */
+ pll = radeon_get_shared_nondp_ppll(crtc);
+ if (pll != ATOM_PPLL_INVALID)
--- /dev/null
+From d5693761b2b4ff530c8af8af9ec55b6eae76e617 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 28 Oct 2013 10:56:23 -0400
+Subject: drm/radeon/si: fix define for MC_SEQ_TRAIN_WAKEUP_CNTL
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit d5693761b2b4ff530c8af8af9ec55b6eae76e617 upstream.
+
+Typo in the register offset.
+
+Noticed-by: Sylvain BERTRAND <sylware@legeek.net>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/sid.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/sid.h
++++ b/drivers/gpu/drm/radeon/sid.h
+@@ -247,7 +247,7 @@
+ #define NOOFGROUPS_SHIFT 12
+ #define NOOFGROUPS_MASK 0x00001000
+
+-#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
++#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
+ #define TRAIN_DONE_D0 (1 << 30)
+ #define TRAIN_DONE_D1 (1 << 31)
+
drm-ttm-fix-ttm_bo_move_memcpy.patch
drm-i915-flush-cursors-harder.patch
drm-nouveau-when-bailing-out-of-a-pushbuf-ioctl-do-not-remove-previous-fence.patch
+drm-radeon-si-fix-define-for-mc_seq_train_wakeup_cntl.patch
+drm-radeon-activate-uvd-clocks-before-sending-the-destroy-msg.patch
+drm-radeon-don-t-share-pplls-on-dce4.1.patch