]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/amdgpu: Fix SDMA TO after GPU reset v3
authorAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Mon, 10 Sep 2018 22:43:58 +0000 (18:43 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 21 Nov 2018 08:21:58 +0000 (09:21 +0100)
[ Upstream commit d8de8260a45aae8f74af77eae9a162bdc0ed48d2 ]

After GPU reset amdgpu_vm_clear_bo triggers VM flush
but job->vm_pd_addr is not set causing SDMA TO.

v2:
Per advise by Christian König avoid flushing VM for jobs where
job->vm_pd_addr wasn't explicitly set.

v3:
Shortcut vm_flush_needed early.

Fixes cbd5285 drm/amdgpu: move setting the GART addr into TTM.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index 2bd56760c7441fdc720d3a469fef424ae39741ea..b1cd8e9649b9b08daeed6acd007cbab24d1d2cf4 100644 (file)
@@ -62,6 +62,7 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
        amdgpu_sync_create(&(*job)->sync);
        amdgpu_sync_create(&(*job)->sched_sync);
        (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
+       (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
 
        return 0;
 }
index c31fff32a32152d88c01ee219b77cd45dfe9718f..eb0ae9726cf7986a6f3954f104d0bb4bdb1286dd 100644 (file)
@@ -631,7 +631,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
        }
 
        gds_switch_needed &= !!ring->funcs->emit_gds_switch;
-       vm_flush_needed &= !!ring->funcs->emit_vm_flush;
+       vm_flush_needed &= !!ring->funcs->emit_vm_flush  &&
+                       job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
        pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
                ring->funcs->emit_wreg;