riscv: dts: sophgo: Add initial SG2002 SoC device tree

Add initial device tree for the SG2002 RISC-V SoC by SOPHGO.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20241010-sg2002-v5-1-a0f2e582b932@bootlin.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
new file mode 100644 (file)
index 0000000..242fde8
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/pinctrl-sg2002.h>
+#include "cv18xx.dtsi"
+
+/ {
+       compatible = "sophgo,sg2002";
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x80000000 0x10000000>;
+       };
+
+       soc {
+               pinctrl: pinctrl@3008000 {
+                       compatible = "sophgo,sg2002-pinctrl";
+                       reg = <0x03001000 0x1000>,
+                             <0x05027000 0x1000>;
+                       reg-names = "sys", "rtc";
+               };
+       };
+};
+
+&plic {
+       compatible = "sophgo,sg2002-plic", "thead,c900-plic";
+};
+
+&clint {
+       compatible = "sophgo,sg2002-clint", "thead,c900-clint";
+};
+
+&clk {
+       compatible = "sophgo,sg2000-clk";
+};
+
+&sdhci0 {
+       compatible = "sophgo,sg2002-dwcmshc";
+};