]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
PCI: imx6: Add missing reference clock disable logic
authorRichard Zhu <hongxing.zhu@nxp.com>
Tue, 26 Nov 2024 07:56:58 +0000 (15:56 +0800)
committerBjorn Helgaas <bhelgaas@google.com>
Thu, 16 Jan 2025 20:29:38 +0000 (14:29 -0600)
Ensure the *_enable_ref_clk() function is symmetric by addressing missing
disable parts on some platforms.

Fixes: d0a75c791f98 ("PCI: imx6: Factor out ref clock disable to match enable")
Link: https://lore.kernel.org/r/20241126075702.4099164-7-hongxing.zhu@nxp.com
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Krzysztof WilczyƄski <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
drivers/pci/controller/dwc/pci-imx6.c

index 261c2ae5f218c0ea3226c8c219f083d35403c17c..e98e1894e91dfa89343b12565ab1969ef36cb78b 100644 (file)
@@ -600,10 +600,9 @@ static int imx_pcie_attach_pd(struct device *dev)
 
 static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 {
-       if (enable)
-               regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
-                                 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
-
+       regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
+                          IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
+                          enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
        return 0;
 }
 
@@ -632,19 +631,20 @@ static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 {
        int offset = imx_pcie_grp_offset(imx_pcie);
 
-       if (enable) {
-               regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
-               regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
-       }
-
+       regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
+                          IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
+                          enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE);
+       regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
+                          IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
+                          enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
        return 0;
 }
 
 static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 {
-       if (!enable)
-               regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
-                               IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
+       regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
+                          IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
+                          enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
        return 0;
 }