x86: don't use VexWIG in SSE2AVX templates

Several years ago it was decided that SSE2AVX templates should not be
sensitive to -mvexwig= (upon my suggestion to consistently make all
sensitive as long as they don't require a specific setting of VEX.W).
Adjust the four that still are, switching to use of Vex128 at the same
time.

diff --git a/gas/testsuite/gas/i386/x86-64-sse2avx.d b/gas/testsuite/gas/i386/x86-64-sse2avx.d
index ea68c7deb5bec159fd14e5949665237c3e997795..18036fb5a2ad3aaeef1837a9b16ebda1ed374bb4 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-sse2avx.d
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx.d
@@ -655,7 +655,7 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    c5 f9 50 cc             vmovmskpd %xmm4,%ecx
 [      ]*[a-f0-9]+:    c5 f8 50 cc             vmovmskps %xmm4,%ecx
 [      ]*[a-f0-9]+:    c5 f9 d7 cc             vpmovmskb %xmm4,%ecx
-[      ]*[a-f0-9]+:    c4 e3 79 17 e1 64       vextractps \$0x64,%xmm4,%ecx
+[      ]*[a-f0-9]+:    c4 e3 f9 17 e1 64       vextractps \$0x64,%xmm4,%ecx
 [      ]*[a-f0-9]+:    c4 e3 79 17 21 64       vextractps \$0x64,%xmm4,\(%rcx\)
 [      ]*[a-f0-9]+:    c4 e3 79 16 e1 64       vpextrd \$0x64,%xmm4,%ecx
 [      ]*[a-f0-9]+:    c4 e3 79 16 21 64       vpextrd \$0x64,%xmm4,\(%rcx\)
@@ -1291,7 +1291,7 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    c5 f9 50 cc             vmovmskpd %xmm4,%ecx
 [      ]*[a-f0-9]+:    c5 f8 50 cc             vmovmskps %xmm4,%ecx
 [      ]*[a-f0-9]+:    c5 f9 d7 cc             vpmovmskb %xmm4,%ecx
-[      ]*[a-f0-9]+:    c4 e3 79 17 e1 64       vextractps \$0x64,%xmm4,%ecx
+[      ]*[a-f0-9]+:    c4 e3 f9 17 e1 64       vextractps \$0x64,%xmm4,%ecx
 [      ]*[a-f0-9]+:    c4 e3 79 17 21 64       vextractps \$0x64,%xmm4,\(%rcx\)
 [      ]*[a-f0-9]+:    c4 e3 79 16 e1 64       vpextrd \$0x64,%xmm4,%ecx
 [      ]*[a-f0-9]+:    c4 e3 79 16 21 64       vpextrd \$0x64,%xmm4,\(%rcx\)

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 848036a11621b4e1a739ca31ddd769cb1c820fcd..c22d08c84daf9952460238fb8256392245dc0127 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1096,8 +1096,8 @@ movd, 0x660f6e, SSE2&x64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegXMM }
 // The MMX templates have to remain after at least the SSE2AVX ones.
 movd, 0xf6e, MMX, D|Modrm|IgnoreSize|NoSuf, { Reg32|Unspecified|BaseIndex, RegMMX }
 movd, 0xf6e, MMX&x64, D|Modrm|NoSuf|Size64, { Reg64|BaseIndex, RegMMX }
-movq, 0xf37e, AVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-movq, 0x66d6, AVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
+movq, 0xf37e, AVX, Load|Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
+movq, 0x66d6, AVX, Modrm|Vex128|Space0F|VexW0|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
 movq, 0x666e, AVX&x64, D|Modrm|Vex=1|Space0F|VexW1|NoSuf|Size64|SSE2AVX, { Reg64|Unspecified|BaseIndex, RegXMM }
 movq, 0xf30f7e, SSE2, Load|Modrm|NoSuf, { Unspecified|Qword|BaseIndex|RegXMM, RegXMM }
 movq, 0x660fd6, SSE2, Modrm|NoSuf, { RegXMM, Unspecified|Qword|BaseIndex|RegXMM }
@@ -1446,8 +1446,8 @@ blendvp<sd>, 0x664a | <sd:opc>, AVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|NoSuf|
 blendvp<sd>, 0x660f3814 | <sd:opc>, SSE4_1, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM }
 blendvp<sd>, 0x660f3814 | <sd:opc>, SSE4_1, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
 dpp<sd><sse41>, 0x660f3a40 | <sd:opc>, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM }
-extractps, 0x6617, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex }
-extractps, 0x6617, AVX&x64, RegMem|Vex|Space0F3A|VexWIG|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64 }
+extractps, 0x6617, AVX, Modrm|Vex128|Space0F3A|VexW0|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex }
+extractps, 0x6617, AVX&x64, RegMem|Vex128|Space0F3A|VexW1|NoSuf|SSE2AVX, { Imm8, RegXMM, Reg64 }
 extractps, 0x660f3a17, SSE4_1, Modrm|IgnoreSize|NoSuf, { Imm8, RegXMM, Reg32|Unspecified|BaseIndex }
 extractps, 0x660f3a17, SSE4_1&x64, RegMem|NoSuf|NoRex64, { Imm8, RegXMM, Reg64 }
 insertps<sse41>, 0x660f3a21, <sse41:cpu>, Modrm|<sse41:attr>|<sse41:vvvv>|NoSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 7bb251776ff7e38eb23e35ce5afb326379575e42..d7b851d81e93bb005cb0f480c80d929c09f79c0a 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -7258,7 +7258,7 @@ static const insn_template i386_optab[] =
          0, 0, 0, 0, 0, 0 } } } },
   { MN_movq, 0x7e, 2, SPACE_0F, None,
     { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
-      0, 0, 0, 1, 0, 3, 2, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+      0, 0, 0, 1, 0, 1, 2, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
       0 },
     { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -7268,7 +7268,7 @@ static const insn_template i386_optab[] =
          1, 0, 0, 0, 0, 0 } } } },
   { MN_movq, 0xd6, 2, SPACE_0F, None,
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
-      0, 0, 0, 1, 0, 3, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+      0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
       0 },
     { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -13536,7 +13536,7 @@ static const insn_template i386_optab[] =
          1, 0, 0, 0, 0, 0 } } } },
   { MN_extractps, 0x17, 3, SPACE_0F3A, None,
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
-      0, 0, 0, 1, 0, 3, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+      0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
       0 },
     { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
@@ -13548,7 +13548,7 @@ static const insn_template i386_optab[] =
          0, 0, 0, 0, 1, 0 } } } },
   { MN_extractps, 0x17, 3, SPACE_0F3A, None,
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0,
-      0, 0, 0, 1, 0, 3, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+      0, 0, 0, 1, 0, 2, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
       0 },
     { { 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0 } },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },