indent_style = space
indent_size = 4
+[*.{s,S}]
+indent_style = tab
+indent_size = 8
+file_type_emacs = asm
+
[*.{vert,frag}]
file_type_emacs = glsl
# Run check-tcg against softmmu targets
- env:
- - CONFIG="--target-list=xtensa-softmmu,arm-softmmu"
+ - CONFIG="--target-list=xtensa-softmmu,arm-softmmu,aarch64-softmmu,alpha-softmmu"
- TEST_CMD="make -j3 check-tcg V=1"
S: Maintained
F: hw/alpha/
F: hw/isa/smc37c669-superio.c
+F: tests/tcg/alpha/system/
ARM Machines
------------
R: Aleksandar Rikalo <arikalo@wavecomp.com>
S: Maintained
F: hw/mips/mips_malta.c
+F: tests/acceptance/linux_ssh_mips_malta.py
Mipssim
M: Aleksandar Markovic <amarkovic@wavecomp.com>
F: contrib/rdmacm-mux/*
F: qapi/rdma.json
+Semihosting
+M: Alex Bennée <alex.bennee@linaro.org>
+L: qemu-devel@nongnu.org
+S: Maintained
+F: hw/semihosting/
+F: include/hw/semihosting/
+
Build and test automation
-------------------------
Build and test automation
%/coverage-report.html:
@mkdir -p $*
$(call quiet-command,\
- gcovr -r $(SRC_PATH) --object-directory $(BUILD_PATH) \
+ gcovr -r $(SRC_PATH) \
+ $(foreach t, $(TARGET_DIRS), --object-directory $(BUILD_DIR)/$(t)) \
+ --object-directory $(BUILD_DIR) \
-p --html --html-details -o $@, \
"GEN", "coverage-report.html")
trace-events-subdirs += hw/watchdog
trace-events-subdirs += hw/xen
trace-events-subdirs += hw/gpio
+trace-events-subdirs += hw/riscv
trace-events-subdirs += migration
trace-events-subdirs += net
trace-events-subdirs += ui
generated-files-y += config-target.h
Makefile: $(generated-files-y)
+
+# Reports/Analysis
+#
+# The target specific coverage report only cares about target specific
+# blobs and not the shared code.
+#
+
+%/coverage-report.html:
+ @mkdir -p $*
+ $(call quiet-command,\
+ gcovr -r $(SRC_PATH) --object-directory $(CURDIR) \
+ -p --html --html-details -o $@, \
+ "GEN", "coverage-report.html")
+
+.PHONY: coverage-report
+coverage-report: $(CURDIR)/reports/coverage/coverage-report.html
}
}
+/*
+ * This function steals the reference to child_bs from the caller.
+ * That reference is later dropped by bdrv_root_unref_child().
+ *
+ * On failure NULL is returned, errp is set and the reference to
+ * child_bs is also dropped.
+ */
BdrvChild *bdrv_root_attach_child(BlockDriverState *child_bs,
const char *child_name,
const BdrvChildRole *child_role,
ret = bdrv_check_update_perm(child_bs, NULL, perm, shared_perm, NULL, errp);
if (ret < 0) {
bdrv_abort_perm_update(child_bs);
+ bdrv_unref(child_bs);
return NULL;
}
return child;
}
+/*
+ * This function transfers the reference to child_bs from the caller
+ * to parent_bs. That reference is later dropped by parent_bs on
+ * bdrv_close() or if someone calls bdrv_unref_child().
+ *
+ * On failure NULL is returned, errp is set and the reference to
+ * child_bs is also dropped.
+ */
BdrvChild *bdrv_attach_child(BlockDriverState *parent_bs,
BlockDriverState *child_bs,
const char *child_name,
/* If backing_hd was already part of bs's backing chain, and
* inherits_from pointed recursively to bs then let's update it to
* point directly to bs (else it will become NULL). */
- if (update_inherits_from) {
+ if (bs->backing && update_inherits_from) {
backing_hd->inherits_from = bs;
}
- if (!bs->backing) {
- bdrv_unref(backing_hd);
- }
out:
bdrv_refresh_limits(bs, NULL);
const BdrvChildRole *child_role,
bool allow_none, Error **errp)
{
- BdrvChild *c;
BlockDriverState *bs;
bs = bdrv_open_child_bs(filename, options, bdref_key, parent, child_role,
return NULL;
}
- c = bdrv_attach_child(parent, bs, bdref_key, child_role, errp);
- if (!c) {
- bdrv_unref(bs);
- return NULL;
- }
-
- return c;
+ return bdrv_attach_child(parent, bs, bdref_key, child_role, errp);
}
/* TODO Future callers may need to specify parent/child_role in order for
bs->drv = NULL;
}
- bdrv_set_backing_hd(bs, NULL, &error_abort);
-
- if (bs->file != NULL) {
- bdrv_unref_child(bs, bs->file);
- bs->file = NULL;
- }
-
QLIST_FOREACH_SAFE(child, &bs->children, next, next) {
- /* TODO Remove bdrv_unref() from drivers' close function and use
- * bdrv_unref_child() here */
- if (child->bs->inherits_from == bs) {
- child->bs->inherits_from = NULL;
- }
- bdrv_detach_child(child);
+ bdrv_unref_child(bs, child);
}
+ bs->backing = NULL;
+ bs->file = NULL;
g_free(bs->opaque);
bs->opaque = NULL;
atomic_set(&bs->copy_on_read, 0);
block-obj-$(CONFIG_VVFAT) += vvfat.o
block-obj-$(CONFIG_DMG) += dmg.o
-block-obj-y += qcow2.o qcow2-refcount.o qcow2-cluster.o qcow2-snapshot.o qcow2-cache.o qcow2-bitmap.o
+block-obj-y += qcow2.o qcow2-refcount.o qcow2-cluster.o qcow2-snapshot.o qcow2-cache.o qcow2-bitmap.o qcow2-threads.o
block-obj-$(CONFIG_QED) += qed.o qed-l2-cache.o qed-table.o qed-cluster.o
block-obj-$(CONFIG_QED) += qed-check.o
block-obj-y += vhdx.o vhdx-endian.o vhdx-log.o
int read_flags = is_write_notifier ? BDRV_REQ_NO_SERIALISING : 0;
int write_flags = job->serialize_target_writes ? BDRV_REQ_SERIALISING : 0;
- hbitmap_reset(job->copy_bitmap, start / job->cluster_size, 1);
+ assert(QEMU_IS_ALIGNED(start, job->cluster_size));
+ hbitmap_reset(job->copy_bitmap, start, job->cluster_size);
nbytes = MIN(job->cluster_size, job->len - start);
if (!*bounce_buffer) {
*bounce_buffer = blk_blockalign(blk, job->cluster_size);
return nbytes;
fail:
- hbitmap_set(job->copy_bitmap, start / job->cluster_size, 1);
+ hbitmap_set(job->copy_bitmap, start, job->cluster_size);
return ret;
}
int write_flags = job->serialize_target_writes ? BDRV_REQ_SERIALISING : 0;
assert(QEMU_IS_ALIGNED(job->copy_range_size, job->cluster_size));
+ assert(QEMU_IS_ALIGNED(start, job->cluster_size));
nbytes = MIN(job->copy_range_size, end - start);
nr_clusters = DIV_ROUND_UP(nbytes, job->cluster_size);
- hbitmap_reset(job->copy_bitmap, start / job->cluster_size,
- nr_clusters);
+ hbitmap_reset(job->copy_bitmap, start, job->cluster_size * nr_clusters);
ret = blk_co_copy_range(blk, start, job->target, start, nbytes,
read_flags, write_flags);
if (ret < 0) {
trace_backup_do_cow_copy_range_fail(job, start, ret);
- hbitmap_set(job->copy_bitmap, start / job->cluster_size,
- nr_clusters);
+ hbitmap_set(job->copy_bitmap, start, job->cluster_size * nr_clusters);
return ret;
}
cow_request_begin(&cow_request, job, start, end);
while (start < end) {
- if (!hbitmap_get(job->copy_bitmap, start / job->cluster_size)) {
+ if (!hbitmap_get(job->copy_bitmap, start)) {
trace_backup_do_cow_skip(job, start);
start += job->cluster_size;
continue; /* already copied */
assert(s->target);
blk_unref(s->target);
s->target = NULL;
+
+ if (s->copy_bitmap) {
+ hbitmap_free(s->copy_bitmap);
+ s->copy_bitmap = NULL;
+ }
}
void backup_do_checkpoint(BlockJob *job, Error **errp)
{
BackupBlockJob *backup_job = container_of(job, BackupBlockJob, common);
- int64_t len;
assert(block_job_driver(job) == &backup_job_driver);
return;
}
- len = DIV_ROUND_UP(backup_job->len, backup_job->cluster_size);
- hbitmap_set(backup_job->copy_bitmap, 0, len);
+ hbitmap_set(backup_job->copy_bitmap, 0, backup_job->len);
}
static void backup_drain(BlockJob *job)
return false;
}
-static int coroutine_fn backup_run_incremental(BackupBlockJob *job)
+static bool bdrv_is_unallocated_range(BlockDriverState *bs,
+ int64_t offset, int64_t bytes)
+{
+ int64_t end = offset + bytes;
+
+ while (offset < end && !bdrv_is_allocated(bs, offset, bytes, &bytes)) {
+ if (bytes == 0) {
+ return true;
+ }
+ offset += bytes;
+ bytes = end - offset;
+ }
+
+ return offset >= end;
+}
+
+static int coroutine_fn backup_loop(BackupBlockJob *job)
{
int ret;
bool error_is_read;
- int64_t cluster;
+ int64_t offset;
HBitmapIter hbi;
+ BlockDriverState *bs = blk_bs(job->common.blk);
hbitmap_iter_init(&hbi, job->copy_bitmap, 0);
- while ((cluster = hbitmap_iter_next(&hbi)) != -1) {
+ while ((offset = hbitmap_iter_next(&hbi)) != -1) {
+ if (job->sync_mode == MIRROR_SYNC_MODE_TOP &&
+ bdrv_is_unallocated_range(bs, offset, job->cluster_size))
+ {
+ hbitmap_reset(job->copy_bitmap, offset, job->cluster_size);
+ continue;
+ }
+
do {
if (yield_and_check(job)) {
return 0;
}
- ret = backup_do_cow(job, cluster * job->cluster_size,
+ ret = backup_do_cow(job, offset,
job->cluster_size, &error_is_read, false);
if (ret < 0 && backup_error_action(job, error_is_read, -ret) ==
BLOCK_ERROR_ACTION_REPORT)
/* init copy_bitmap from sync_bitmap */
static void backup_incremental_init_copy_bitmap(BackupBlockJob *job)
{
- BdrvDirtyBitmapIter *dbi;
- int64_t offset;
- int64_t end = DIV_ROUND_UP(bdrv_dirty_bitmap_size(job->sync_bitmap),
- job->cluster_size);
+ uint64_t offset = 0;
+ uint64_t bytes = job->len;
- dbi = bdrv_dirty_iter_new(job->sync_bitmap);
- while ((offset = bdrv_dirty_iter_next(dbi)) != -1) {
- int64_t cluster = offset / job->cluster_size;
- int64_t next_cluster;
-
- offset += bdrv_dirty_bitmap_granularity(job->sync_bitmap);
- if (offset >= bdrv_dirty_bitmap_size(job->sync_bitmap)) {
- hbitmap_set(job->copy_bitmap, cluster, end - cluster);
- break;
- }
+ while (bdrv_dirty_bitmap_next_dirty_area(job->sync_bitmap,
+ &offset, &bytes))
+ {
+ hbitmap_set(job->copy_bitmap, offset, bytes);
- offset = bdrv_dirty_bitmap_next_zero(job->sync_bitmap, offset,
- UINT64_MAX);
- if (offset == -1) {
- hbitmap_set(job->copy_bitmap, cluster, end - cluster);
+ offset += bytes;
+ if (offset >= job->len) {
break;
}
-
- next_cluster = DIV_ROUND_UP(offset, job->cluster_size);
- hbitmap_set(job->copy_bitmap, cluster, next_cluster - cluster);
- if (next_cluster >= end) {
- break;
- }
-
- bdrv_set_dirty_iter(dbi, next_cluster * job->cluster_size);
+ bytes = job->len - offset;
}
/* TODO job_progress_set_remaining() would make more sense */
job_progress_update(&job->common.job,
- job->len - hbitmap_count(job->copy_bitmap) * job->cluster_size);
-
- bdrv_dirty_iter_free(dbi);
+ job->len - hbitmap_count(job->copy_bitmap));
}
static int coroutine_fn backup_run(Job *job, Error **errp)
{
BackupBlockJob *s = container_of(job, BackupBlockJob, common.job);
BlockDriverState *bs = blk_bs(s->common.blk);
- int64_t offset, nb_clusters;
int ret = 0;
QLIST_INIT(&s->inflight_reqs);
qemu_co_rwlock_init(&s->flush_rwlock);
- nb_clusters = DIV_ROUND_UP(s->len, s->cluster_size);
job_progress_set_remaining(job, s->len);
- s->copy_bitmap = hbitmap_alloc(nb_clusters, 0);
if (s->sync_mode == MIRROR_SYNC_MODE_INCREMENTAL) {
backup_incremental_init_copy_bitmap(s);
} else {
- hbitmap_set(s->copy_bitmap, 0, nb_clusters);
+ hbitmap_set(s->copy_bitmap, 0, s->len);
}
-
s->before_write.notify = backup_before_write_notify;
bdrv_add_before_write_notifier(bs, &s->before_write);
* notify callback service CoW requests. */
job_yield(job);
}
- } else if (s->sync_mode == MIRROR_SYNC_MODE_INCREMENTAL) {
- ret = backup_run_incremental(s);
} else {
- /* Both FULL and TOP SYNC_MODE's require copying.. */
- for (offset = 0; offset < s->len;
- offset += s->cluster_size) {
- bool error_is_read;
- int alloced = 0;
-
- if (yield_and_check(s)) {
- break;
- }
-
- if (s->sync_mode == MIRROR_SYNC_MODE_TOP) {
- int i;
- int64_t n;
-
- /* Check to see if these blocks are already in the
- * backing file. */
-
- for (i = 0; i < s->cluster_size;) {
- /* bdrv_is_allocated() only returns true/false based
- * on the first set of sectors it comes across that
- * are are all in the same state.
- * For that reason we must verify each sector in the
- * backup cluster length. We end up copying more than
- * needed but at some point that is always the case. */
- alloced =
- bdrv_is_allocated(bs, offset + i,
- s->cluster_size - i, &n);
- i += n;
-
- if (alloced || n == 0) {
- break;
- }
- }
-
- /* If the above loop never found any sectors that are in
- * the topmost image, skip this backup. */
- if (alloced == 0) {
- continue;
- }
- }
- /* FULL sync mode we copy the whole drive. */
- if (alloced < 0) {
- ret = alloced;
- } else {
- ret = backup_do_cow(s, offset, s->cluster_size,
- &error_is_read, false);
- }
- if (ret < 0) {
- /* Depending on error action, fail now or retry cluster */
- BlockErrorAction action =
- backup_error_action(s, error_is_read, -ret);
- if (action == BLOCK_ERROR_ACTION_REPORT) {
- break;
- } else {
- offset -= s->cluster_size;
- continue;
- }
- }
- }
+ ret = backup_loop(s);
}
notifier_with_return_remove(&s->before_write);
/* wait until pending backup_do_cow() calls have completed */
qemu_co_rwlock_wrlock(&s->flush_rwlock);
qemu_co_rwlock_unlock(&s->flush_rwlock);
- hbitmap_free(s->copy_bitmap);
return ret;
}
.drain = backup_drain,
};
+static int64_t backup_calculate_cluster_size(BlockDriverState *target,
+ Error **errp)
+{
+ int ret;
+ BlockDriverInfo bdi;
+
+ /*
+ * If there is no backing file on the target, we cannot rely on COW if our
+ * backup cluster size is smaller than the target cluster size. Even for
+ * targets with a backing file, try to avoid COW if possible.
+ */
+ ret = bdrv_get_info(target, &bdi);
+ if (ret == -ENOTSUP && !target->backing) {
+ /* Cluster size is not defined */
+ warn_report("The target block device doesn't provide "
+ "information about the block size and it doesn't have a "
+ "backing file. The default block size of %u bytes is "
+ "used. If the actual block size of the target exceeds "
+ "this default, the backup may be unusable",
+ BACKUP_CLUSTER_SIZE_DEFAULT);
+ return BACKUP_CLUSTER_SIZE_DEFAULT;
+ } else if (ret < 0 && !target->backing) {
+ error_setg_errno(errp, -ret,
+ "Couldn't determine the cluster size of the target image, "
+ "which has no backing file");
+ error_append_hint(errp,
+ "Aborting, since this may create an unusable destination image\n");
+ return ret;
+ } else if (ret < 0 && target->backing) {
+ /* Not fatal; just trudge on ahead. */
+ return BACKUP_CLUSTER_SIZE_DEFAULT;
+ }
+
+ return MAX(BACKUP_CLUSTER_SIZE_DEFAULT, bdi.cluster_size);
+}
+
BlockJob *backup_job_create(const char *job_id, BlockDriverState *bs,
BlockDriverState *target, int64_t speed,
MirrorSyncMode sync_mode, BdrvDirtyBitmap *sync_bitmap,
JobTxn *txn, Error **errp)
{
int64_t len;
- BlockDriverInfo bdi;
BackupBlockJob *job = NULL;
int ret;
+ int64_t cluster_size;
+ HBitmap *copy_bitmap = NULL;
assert(bs);
assert(target);
goto error;
}
+ cluster_size = backup_calculate_cluster_size(target, errp);
+ if (cluster_size < 0) {
+ goto error;
+ }
+
+ copy_bitmap = hbitmap_alloc(len, ctz32(cluster_size));
+
/* job->len is fixed, so we can't allow resize */
job = block_job_create(job_id, &backup_job_driver, txn, bs,
BLK_PERM_CONSISTENT_READ,
/* Detect image-fleecing (and similar) schemes */
job->serialize_target_writes = bdrv_chain_contains(target, bs);
-
- /* If there is no backing file on the target, we cannot rely on COW if our
- * backup cluster size is smaller than the target cluster size. Even for
- * targets with a backing file, try to avoid COW if possible. */
- ret = bdrv_get_info(target, &bdi);
- if (ret == -ENOTSUP && !target->backing) {
- /* Cluster size is not defined */
- warn_report("The target block device doesn't provide "
- "information about the block size and it doesn't have a "
- "backing file. The default block size of %u bytes is "
- "used. If the actual block size of the target exceeds "
- "this default, the backup may be unusable",
- BACKUP_CLUSTER_SIZE_DEFAULT);
- job->cluster_size = BACKUP_CLUSTER_SIZE_DEFAULT;
- } else if (ret < 0 && !target->backing) {
- error_setg_errno(errp, -ret,
- "Couldn't determine the cluster size of the target image, "
- "which has no backing file");
- error_append_hint(errp,
- "Aborting, since this may create an unusable destination image\n");
- goto error;
- } else if (ret < 0 && target->backing) {
- /* Not fatal; just trudge on ahead. */
- job->cluster_size = BACKUP_CLUSTER_SIZE_DEFAULT;
- } else {
- job->cluster_size = MAX(BACKUP_CLUSTER_SIZE_DEFAULT, bdi.cluster_size);
- }
+ job->cluster_size = cluster_size;
+ job->copy_bitmap = copy_bitmap;
+ copy_bitmap = NULL;
job->use_copy_range = true;
job->copy_range_size = MIN_NON_ZERO(blk_get_max_transfer(job->common.blk),
blk_get_max_transfer(job->target));
return &job->common;
error:
+ if (copy_bitmap) {
+ assert(!job || !job->copy_bitmap);
+ hbitmap_free(copy_bitmap);
+ }
if (sync_bitmap) {
bdrv_reclaim_dirty_bitmap(bs, sync_bitmap, NULL);
}
blk->root = bdrv_root_attach_child(bs, "root", &child_root,
perm, BLK_PERM_ALL, blk, errp);
if (!blk->root) {
- bdrv_unref(bs);
blk_unref(blk);
return NULL;
}
int blk_insert_bs(BlockBackend *blk, BlockDriverState *bs, Error **errp)
{
ThrottleGroupMember *tgm = &blk->public.throttle_group_member;
+ bdrv_ref(bs);
blk->root = bdrv_root_attach_child(bs, "root", &child_root,
blk->perm, blk->shared_perm, blk, errp);
if (blk->root == NULL) {
return -EPERM;
}
- bdrv_ref(bs);
notifier_list_notify(&blk->insert_bs_notifiers, blk);
if (tgm->throttle_state) {
{
bool ret;
- /* only bitmaps from one bds are supported */
- assert(dest->mutex == src->mutex);
-
qemu_mutex_lock(dest->mutex);
+ if (src->mutex != dest->mutex) {
+ qemu_mutex_lock(src->mutex);
+ }
if (bdrv_dirty_bitmap_check(dest, BDRV_BITMAP_DEFAULT, errp)) {
goto out;
out:
qemu_mutex_unlock(dest->mutex);
+ if (src->mutex != dest->mutex) {
+ qemu_mutex_unlock(src->mutex);
+ }
}
#include "qapi/error.h"
#include "qemu/cutils.h"
-#include "block/block_int.h"
#include "qcow2.h"
/* NOTICE: BME here means Bitmaps Extension and used as a namespace for
dir_offset = *offset;
}
- dir = g_try_malloc(dir_size);
+ dir = g_try_malloc0(dir_size);
if (dir == NULL) {
return -ENOMEM;
}
*/
#include "qemu/osdep.h"
-#include "block/block_int.h"
#include "qemu-common.h"
#include "qcow2.h"
#include "trace.h"
#include "qapi/error.h"
#include "qemu-common.h"
-#include "block/block_int.h"
#include "qcow2.h"
#include "qemu/bswap.h"
#include "trace.h"
{
if (bytes && bs->encrypted) {
BDRVQcow2State *s = bs->opaque;
- int64_t offset = (s->crypt_physical_offset ?
- (cluster_offset + offset_in_cluster) :
- (src_cluster_offset + offset_in_cluster));
assert((offset_in_cluster & ~BDRV_SECTOR_MASK) == 0);
assert((bytes & ~BDRV_SECTOR_MASK) == 0);
assert(s->crypto);
- if (qcrypto_block_encrypt(s->crypto, offset, buffer, bytes, NULL) < 0) {
+ if (qcow2_co_encrypt(bs, cluster_offset,
+ src_cluster_offset + offset_in_cluster,
+ buffer, bytes) < 0) {
return false;
}
}
assert(start->offset + start->nb_bytes <= end->offset);
assert(!m->data_qiov || m->data_qiov->size == data_bytes);
- if (start->nb_bytes == 0 && end->nb_bytes == 0) {
+ if ((start->nb_bytes == 0 && end->nb_bytes == 0) || m->skip_cow) {
return 0;
}
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
-#include "block/block_int.h"
#include "qcow2.h"
#include "qemu/range.h"
#include "qemu/bswap.h"
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "block/block_int.h"
#include "qcow2.h"
#include "qemu/bswap.h"
#include "qemu/error-report.h"
--- /dev/null
+/*
+ * Threaded data processing for Qcow2: compression, encryption
+ *
+ * Copyright (c) 2004-2006 Fabrice Bellard
+ * Copyright (c) 2018 Virtuozzo International GmbH. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+
+#define ZLIB_CONST
+#include <zlib.h>
+
+#include "qcow2.h"
+#include "block/thread-pool.h"
+#include "crypto.h"
+
+static int coroutine_fn
+qcow2_co_process(BlockDriverState *bs, ThreadPoolFunc *func, void *arg)
+{
+ int ret;
+ BDRVQcow2State *s = bs->opaque;
+ ThreadPool *pool = aio_get_thread_pool(bdrv_get_aio_context(bs));
+
+ qemu_co_mutex_lock(&s->lock);
+ while (s->nb_threads >= QCOW2_MAX_THREADS) {
+ qemu_co_queue_wait(&s->thread_task_queue, &s->lock);
+ }
+ s->nb_threads++;
+ qemu_co_mutex_unlock(&s->lock);
+
+ ret = thread_pool_submit_co(pool, func, arg);
+
+ qemu_co_mutex_lock(&s->lock);
+ s->nb_threads--;
+ qemu_co_queue_next(&s->thread_task_queue);
+ qemu_co_mutex_unlock(&s->lock);
+
+ return ret;
+}
+
+
+/*
+ * Compression
+ */
+
+typedef ssize_t (*Qcow2CompressFunc)(void *dest, size_t dest_size,
+ const void *src, size_t src_size);
+typedef struct Qcow2CompressData {
+ void *dest;
+ size_t dest_size;
+ const void *src;
+ size_t src_size;
+ ssize_t ret;
+
+ Qcow2CompressFunc func;
+} Qcow2CompressData;
+
+/*
+ * qcow2_compress()
+ *
+ * @dest - destination buffer, @dest_size bytes
+ * @src - source buffer, @src_size bytes
+ *
+ * Returns: compressed size on success
+ * -ENOMEM destination buffer is not enough to store compressed data
+ * -EIO on any other error
+ */
+static ssize_t qcow2_compress(void *dest, size_t dest_size,
+ const void *src, size_t src_size)
+{
+ ssize_t ret;
+ z_stream strm;
+
+ /* best compression, small window, no zlib header */
+ memset(&strm, 0, sizeof(strm));
+ ret = deflateInit2(&strm, Z_DEFAULT_COMPRESSION, Z_DEFLATED,
+ -12, 9, Z_DEFAULT_STRATEGY);
+ if (ret != Z_OK) {
+ return -EIO;
+ }
+
+ /*
+ * strm.next_in is not const in old zlib versions, such as those used on
+ * OpenBSD/NetBSD, so cast the const away
+ */
+ strm.avail_in = src_size;
+ strm.next_in = (void *) src;
+ strm.avail_out = dest_size;
+ strm.next_out = dest;
+
+ ret = deflate(&strm, Z_FINISH);
+ if (ret == Z_STREAM_END) {
+ ret = dest_size - strm.avail_out;
+ } else {
+ ret = (ret == Z_OK ? -ENOMEM : -EIO);
+ }
+
+ deflateEnd(&strm);
+
+ return ret;
+}
+
+/*
+ * qcow2_decompress()
+ *
+ * Decompress some data (not more than @src_size bytes) to produce exactly
+ * @dest_size bytes.
+ *
+ * @dest - destination buffer, @dest_size bytes
+ * @src - source buffer, @src_size bytes
+ *
+ * Returns: 0 on success
+ * -1 on fail
+ */
+static ssize_t qcow2_decompress(void *dest, size_t dest_size,
+ const void *src, size_t src_size)
+{
+ int ret = 0;
+ z_stream strm;
+
+ memset(&strm, 0, sizeof(strm));
+ strm.avail_in = src_size;
+ strm.next_in = (void *) src;
+ strm.avail_out = dest_size;
+ strm.next_out = dest;
+
+ ret = inflateInit2(&strm, -12);
+ if (ret != Z_OK) {
+ return -1;
+ }
+
+ ret = inflate(&strm, Z_FINISH);
+ if ((ret != Z_STREAM_END && ret != Z_BUF_ERROR) || strm.avail_out != 0) {
+ /*
+ * We approve Z_BUF_ERROR because we need @dest buffer to be filled, but
+ * @src buffer may be processed partly (because in qcow2 we know size of
+ * compressed data with precision of one sector)
+ */
+ ret = -1;
+ }
+
+ inflateEnd(&strm);
+
+ return ret;
+}
+
+static int qcow2_compress_pool_func(void *opaque)
+{
+ Qcow2CompressData *data = opaque;
+
+ data->ret = data->func(data->dest, data->dest_size,
+ data->src, data->src_size);
+
+ return 0;
+}
+
+static ssize_t coroutine_fn
+qcow2_co_do_compress(BlockDriverState *bs, void *dest, size_t dest_size,
+ const void *src, size_t src_size, Qcow2CompressFunc func)
+{
+ Qcow2CompressData arg = {
+ .dest = dest,
+ .dest_size = dest_size,
+ .src = src,
+ .src_size = src_size,
+ .func = func,
+ };
+
+ qcow2_co_process(bs, qcow2_compress_pool_func, &arg);
+
+ return arg.ret;
+}
+
+ssize_t coroutine_fn
+qcow2_co_compress(BlockDriverState *bs, void *dest, size_t dest_size,
+ const void *src, size_t src_size)
+{
+ return qcow2_co_do_compress(bs, dest, dest_size, src, src_size,
+ qcow2_compress);
+}
+
+ssize_t coroutine_fn
+qcow2_co_decompress(BlockDriverState *bs, void *dest, size_t dest_size,
+ const void *src, size_t src_size)
+{
+ return qcow2_co_do_compress(bs, dest, dest_size, src, src_size,
+ qcow2_decompress);
+}
+
+
+/*
+ * Cryptography
+ */
+
+/*
+ * Qcow2EncDecFunc: common prototype of qcrypto_block_encrypt() and
+ * qcrypto_block_decrypt() functions.
+ */
+typedef int (*Qcow2EncDecFunc)(QCryptoBlock *block, uint64_t offset,
+ uint8_t *buf, size_t len, Error **errp);
+
+typedef struct Qcow2EncDecData {
+ QCryptoBlock *block;
+ uint64_t offset;
+ uint8_t *buf;
+ size_t len;
+
+ Qcow2EncDecFunc func;
+} Qcow2EncDecData;
+
+static int qcow2_encdec_pool_func(void *opaque)
+{
+ Qcow2EncDecData *data = opaque;
+
+ return data->func(data->block, data->offset, data->buf, data->len, NULL);
+}
+
+static int coroutine_fn
+qcow2_co_encdec(BlockDriverState *bs, uint64_t file_cluster_offset,
+ uint64_t offset, void *buf, size_t len, Qcow2EncDecFunc func)
+{
+ BDRVQcow2State *s = bs->opaque;
+ Qcow2EncDecData arg = {
+ .block = s->crypto,
+ .offset = s->crypt_physical_offset ?
+ file_cluster_offset + offset_into_cluster(s, offset) :
+ offset,
+ .buf = buf,
+ .len = len,
+ .func = func,
+ };
+
+ return qcow2_co_process(bs, qcow2_encdec_pool_func, &arg);
+}
+
+int coroutine_fn
+qcow2_co_encrypt(BlockDriverState *bs, uint64_t file_cluster_offset,
+ uint64_t offset, void *buf, size_t len)
+{
+ return qcow2_co_encdec(bs, file_cluster_offset, offset, buf, len,
+ qcrypto_block_encrypt);
+}
+
+int coroutine_fn
+qcow2_co_decrypt(BlockDriverState *bs, uint64_t file_cluster_offset,
+ uint64_t offset, void *buf, size_t len)
+{
+ return qcow2_co_encdec(bs, file_cluster_offset, offset, buf, len,
+ qcrypto_block_decrypt);
+}
#include "qemu/osdep.h"
-#define ZLIB_CONST
-#include <zlib.h>
-
-#include "block/block_int.h"
#include "block/qdict.h"
#include "sysemu/block-backend.h"
#include "qemu/module.h"
#include "qapi/qobject-input-visitor.h"
#include "qapi/qapi-visit-block-core.h"
#include "crypto.h"
-#include "block/thread-pool.h"
/*
Differences with QCOW:
}
s->crypto = qcrypto_block_open(s->crypto_opts, "encrypt.",
qcow2_crypto_hdr_read_func,
- bs, cflags, 1, errp);
+ bs, cflags, QCOW2_MAX_THREADS, errp);
if (!s->crypto) {
return -EINVAL;
}
cflags |= QCRYPTO_BLOCK_OPEN_NO_IO;
}
s->crypto = qcrypto_block_open(s->crypto_opts, "encrypt.",
- NULL, NULL, cflags, 1, errp);
+ NULL, NULL, cflags,
+ QCOW2_MAX_THREADS, errp);
if (!s->crypto) {
ret = -EINVAL;
goto fail;
}
#endif
- qemu_co_queue_init(&s->compress_wait_queue);
+ qemu_co_queue_init(&s->thread_task_queue);
return ret;
qemu_iovec_init(&hd_qiov, qiov->niov);
- qemu_co_mutex_lock(&s->lock);
-
while (bytes != 0) {
/* prepare next request */
QCOW_MAX_CRYPT_CLUSTERS * s->cluster_size);
}
+ qemu_co_mutex_lock(&s->lock);
ret = qcow2_get_cluster_offset(bs, offset, &cur_bytes, &cluster_offset);
+ qemu_co_mutex_unlock(&s->lock);
if (ret < 0) {
goto fail;
}
if (bs->backing) {
BLKDBG_EVENT(bs->file, BLKDBG_READ_BACKING_AIO);
- qemu_co_mutex_unlock(&s->lock);
ret = bdrv_co_preadv(bs->backing, offset, cur_bytes,
&hd_qiov, 0);
- qemu_co_mutex_lock(&s->lock);
if (ret < 0) {
goto fail;
}
break;
case QCOW2_CLUSTER_COMPRESSED:
- qemu_co_mutex_unlock(&s->lock);
ret = qcow2_co_preadv_compressed(bs, cluster_offset,
offset, cur_bytes,
&hd_qiov);
- qemu_co_mutex_lock(&s->lock);
if (ret < 0) {
goto fail;
}
}
BLKDBG_EVENT(bs->file, BLKDBG_READ_AIO);
- qemu_co_mutex_unlock(&s->lock);
ret = bdrv_co_preadv(s->data_file,
cluster_offset + offset_in_cluster,
cur_bytes, &hd_qiov, 0);
- qemu_co_mutex_lock(&s->lock);
if (ret < 0) {
goto fail;
}
assert(s->crypto);
assert((offset & (BDRV_SECTOR_SIZE - 1)) == 0);
assert((cur_bytes & (BDRV_SECTOR_SIZE - 1)) == 0);
- if (qcrypto_block_decrypt(s->crypto,
- (s->crypt_physical_offset ?
- cluster_offset + offset_in_cluster :
- offset),
- cluster_data,
- cur_bytes,
- NULL) < 0) {
+ if (qcow2_co_decrypt(bs, cluster_offset, offset,
+ cluster_data, cur_bytes) < 0) {
ret = -EIO;
goto fail;
}
ret = 0;
fail:
- qemu_co_mutex_unlock(&s->lock);
-
qemu_iovec_destroy(&hd_qiov);
qemu_vfree(cluster_data);
continue;
}
+ /* If COW regions are handled already, skip this too */
+ if (m->skip_cow) {
+ continue;
+ }
+
/* The data (middle) region must be immediately after the
* start region */
if (l2meta_cow_start(m) + m->cow_start.nb_bytes != offset) {
return false;
}
+static bool is_unallocated(BlockDriverState *bs, int64_t offset, int64_t bytes)
+{
+ int64_t nr;
+ return !bytes ||
+ (!bdrv_is_allocated_above(bs, NULL, offset, bytes, &nr) && nr == bytes);
+}
+
+static bool is_zero_cow(BlockDriverState *bs, QCowL2Meta *m)
+{
+ /*
+ * This check is designed for optimization shortcut so it must be
+ * efficient.
+ * Instead of is_zero(), use is_unallocated() as it is faster (but not
+ * as accurate and can result in false negatives).
+ */
+ return is_unallocated(bs, m->offset + m->cow_start.offset,
+ m->cow_start.nb_bytes) &&
+ is_unallocated(bs, m->offset + m->cow_end.offset,
+ m->cow_end.nb_bytes);
+}
+
+static int handle_alloc_space(BlockDriverState *bs, QCowL2Meta *l2meta)
+{
+ BDRVQcow2State *s = bs->opaque;
+ QCowL2Meta *m;
+
+ if (!(s->data_file->bs->supported_zero_flags & BDRV_REQ_NO_FALLBACK)) {
+ return 0;
+ }
+
+ if (bs->encrypted) {
+ return 0;
+ }
+
+ for (m = l2meta; m != NULL; m = m->next) {
+ int ret;
+
+ if (!m->cow_start.nb_bytes && !m->cow_end.nb_bytes) {
+ continue;
+ }
+
+ if (!is_zero_cow(bs, m)) {
+ continue;
+ }
+
+ /*
+ * instead of writing zero COW buffers,
+ * efficiently zero out the whole clusters
+ */
+
+ ret = qcow2_pre_write_overlap_check(bs, 0, m->alloc_offset,
+ m->nb_clusters * s->cluster_size,
+ true);
+ if (ret < 0) {
+ return ret;
+ }
+
+ BLKDBG_EVENT(bs->file, BLKDBG_CLUSTER_ALLOC_SPACE);
+ ret = bdrv_co_pwrite_zeroes(s->data_file, m->alloc_offset,
+ m->nb_clusters * s->cluster_size,
+ BDRV_REQ_NO_FALLBACK);
+ if (ret < 0) {
+ if (ret != -ENOTSUP && ret != -EAGAIN) {
+ return ret;
+ }
+ continue;
+ }
+
+ trace_qcow2_skip_cow(qemu_coroutine_self(), m->offset, m->nb_clusters);
+ m->skip_cow = true;
+ }
+ return 0;
+}
+
static coroutine_fn int qcow2_co_pwritev(BlockDriverState *bs, uint64_t offset,
uint64_t bytes, QEMUIOVector *qiov,
int flags)
ret = qcow2_alloc_cluster_offset(bs, offset, &cur_bytes,
&cluster_offset, &l2meta);
if (ret < 0) {
- goto fail;
+ goto out_locked;
}
assert((cluster_offset & 511) == 0);
+ ret = qcow2_pre_write_overlap_check(bs, 0,
+ cluster_offset + offset_in_cluster,
+ cur_bytes, true);
+ if (ret < 0) {
+ goto out_locked;
+ }
+
+ qemu_co_mutex_unlock(&s->lock);
+
qemu_iovec_reset(&hd_qiov);
qemu_iovec_concat(&hd_qiov, qiov, bytes_done, cur_bytes);
* s->cluster_size);
if (cluster_data == NULL) {
ret = -ENOMEM;
- goto fail;
+ goto out_unlocked;
}
}
QCOW_MAX_CRYPT_CLUSTERS * s->cluster_size);
qemu_iovec_to_buf(&hd_qiov, 0, cluster_data, hd_qiov.size);
- if (qcrypto_block_encrypt(s->crypto,
- (s->crypt_physical_offset ?
- cluster_offset + offset_in_cluster :
- offset),
- cluster_data,
- cur_bytes, NULL) < 0) {
+ if (qcow2_co_encrypt(bs, cluster_offset, offset,
+ cluster_data, cur_bytes) < 0) {
ret = -EIO;
- goto fail;
+ goto out_unlocked;
}
qemu_iovec_reset(&hd_qiov);
qemu_iovec_add(&hd_qiov, cluster_data, cur_bytes);
}
- ret = qcow2_pre_write_overlap_check(bs, 0,
- cluster_offset + offset_in_cluster, cur_bytes, true);
+ /* Try to efficiently initialize the physical space with zeroes */
+ ret = handle_alloc_space(bs, l2meta);
if (ret < 0) {
- goto fail;
+ goto out_unlocked;
}
/* If we need to do COW, check if it's possible to merge the
* If it's not possible (or not necessary) then write the
* guest data now. */
if (!merge_cow(offset, cur_bytes, &hd_qiov, l2meta)) {
- qemu_co_mutex_unlock(&s->lock);
BLKDBG_EVENT(bs->file, BLKDBG_WRITE_AIO);
trace_qcow2_writev_data(qemu_coroutine_self(),
cluster_offset + offset_in_cluster);
ret = bdrv_co_pwritev(s->data_file,
cluster_offset + offset_in_cluster,
cur_bytes, &hd_qiov, 0);
- qemu_co_mutex_lock(&s->lock);
if (ret < 0) {
- goto fail;
+ goto out_unlocked;
}
}
+ qemu_co_mutex_lock(&s->lock);
+
ret = qcow2_handle_l2meta(bs, &l2meta, true);
if (ret) {
- goto fail;
+ goto out_locked;
}
bytes -= cur_bytes;
trace_qcow2_writev_done_part(qemu_coroutine_self(), cur_bytes);
}
ret = 0;
+ goto out_locked;
-fail:
+out_unlocked:
+ qemu_co_mutex_lock(&s->lock);
+
+out_locked:
qcow2_handle_l2meta(bs, &l2meta, false);
qemu_co_mutex_unlock(&s->lock);
return ret;
}
-/*
- * qcow2_compress()
- *
- * @dest - destination buffer, @dest_size bytes
- * @src - source buffer, @src_size bytes
- *
- * Returns: compressed size on success
- * -ENOMEM destination buffer is not enough to store compressed data
- * -EIO on any other error
- */
-static ssize_t qcow2_compress(void *dest, size_t dest_size,
- const void *src, size_t src_size)
-{
- ssize_t ret;
- z_stream strm;
-
- /* best compression, small window, no zlib header */
- memset(&strm, 0, sizeof(strm));
- ret = deflateInit2(&strm, Z_DEFAULT_COMPRESSION, Z_DEFLATED,
- -12, 9, Z_DEFAULT_STRATEGY);
- if (ret != Z_OK) {
- return -EIO;
- }
-
- /* strm.next_in is not const in old zlib versions, such as those used on
- * OpenBSD/NetBSD, so cast the const away */
- strm.avail_in = src_size;
- strm.next_in = (void *) src;
- strm.avail_out = dest_size;
- strm.next_out = dest;
-
- ret = deflate(&strm, Z_FINISH);
- if (ret == Z_STREAM_END) {
- ret = dest_size - strm.avail_out;
- } else {
- ret = (ret == Z_OK ? -ENOMEM : -EIO);
- }
-
- deflateEnd(&strm);
-
- return ret;
-}
-
-/*
- * qcow2_decompress()
- *
- * Decompress some data (not more than @src_size bytes) to produce exactly
- * @dest_size bytes.
- *
- * @dest - destination buffer, @dest_size bytes
- * @src - source buffer, @src_size bytes
- *
- * Returns: 0 on success
- * -1 on fail
- */
-static ssize_t qcow2_decompress(void *dest, size_t dest_size,
- const void *src, size_t src_size)
-{
- int ret = 0;
- z_stream strm;
-
- memset(&strm, 0, sizeof(strm));
- strm.avail_in = src_size;
- strm.next_in = (void *) src;
- strm.avail_out = dest_size;
- strm.next_out = dest;
-
- ret = inflateInit2(&strm, -12);
- if (ret != Z_OK) {
- return -1;
- }
-
- ret = inflate(&strm, Z_FINISH);
- if ((ret != Z_STREAM_END && ret != Z_BUF_ERROR) || strm.avail_out != 0) {
- /* We approve Z_BUF_ERROR because we need @dest buffer to be filled, but
- * @src buffer may be processed partly (because in qcow2 we know size of
- * compressed data with precision of one sector) */
- ret = -1;
- }
-
- inflateEnd(&strm);
-
- return ret;
-}
-
-#define MAX_COMPRESS_THREADS 4
-
-typedef ssize_t (*Qcow2CompressFunc)(void *dest, size_t dest_size,
- const void *src, size_t src_size);
-typedef struct Qcow2CompressData {
- void *dest;
- size_t dest_size;
- const void *src;
- size_t src_size;
- ssize_t ret;
-
- Qcow2CompressFunc func;
-} Qcow2CompressData;
-
-static int qcow2_compress_pool_func(void *opaque)
-{
- Qcow2CompressData *data = opaque;
-
- data->ret = data->func(data->dest, data->dest_size,
- data->src, data->src_size);
-
- return 0;
-}
-
-static void qcow2_compress_complete(void *opaque, int ret)
-{
- qemu_coroutine_enter(opaque);
-}
-
-static ssize_t coroutine_fn
-qcow2_co_do_compress(BlockDriverState *bs, void *dest, size_t dest_size,
- const void *src, size_t src_size, Qcow2CompressFunc func)
-{
- BDRVQcow2State *s = bs->opaque;
- BlockAIOCB *acb;
- ThreadPool *pool = aio_get_thread_pool(bdrv_get_aio_context(bs));
- Qcow2CompressData arg = {
- .dest = dest,
- .dest_size = dest_size,
- .src = src,
- .src_size = src_size,
- .func = func,
- };
-
- while (s->nb_compress_threads >= MAX_COMPRESS_THREADS) {
- qemu_co_queue_wait(&s->compress_wait_queue, NULL);
- }
-
- s->nb_compress_threads++;
- acb = thread_pool_submit_aio(pool, qcow2_compress_pool_func, &arg,
- qcow2_compress_complete,
- qemu_coroutine_self());
-
- if (!acb) {
- s->nb_compress_threads--;
- return -EINVAL;
- }
- qemu_coroutine_yield();
- s->nb_compress_threads--;
- qemu_co_queue_next(&s->compress_wait_queue);
-
- return arg.ret;
-}
-
-static ssize_t coroutine_fn
-qcow2_co_compress(BlockDriverState *bs, void *dest, size_t dest_size,
- const void *src, size_t src_size)
-{
- return qcow2_co_do_compress(bs, dest, dest_size, src, src_size,
- qcow2_compress);
-}
-
-static ssize_t coroutine_fn
-qcow2_co_decompress(BlockDriverState *bs, void *dest, size_t dest_size,
- const void *src, size_t src_size)
-{
- return qcow2_co_do_compress(bs, dest, dest_size, src, src_size,
- qcow2_decompress);
-}
-
/* XXX: put compressed sectors first, then all the cluster aligned
tables to avoid losing bytes in alignment */
static coroutine_fn int
#include "crypto/block.h"
#include "qemu/coroutine.h"
#include "qemu/units.h"
+#include "block/block_int.h"
//#define DEBUG_ALLOC
//#define DEBUG_ALLOC2
uint64_t bitmap_directory_offset;
} QEMU_PACKED Qcow2BitmapHeaderExt;
+#define QCOW2_MAX_THREADS 4
+
typedef struct BDRVQcow2State {
int cluster_bits;
int cluster_size;
char *image_backing_format;
char *image_data_file;
- CoQueue compress_wait_queue;
- int nb_compress_threads;
+ CoQueue thread_task_queue;
+ int nb_threads;
BdrvChild *data_file;
} BDRVQcow2State;
*/
Qcow2COWRegion cow_end;
+ /*
+ * Indicates that COW regions are already handled and do not require
+ * any more processing.
+ */
+ bool skip_cow;
+
/**
* The I/O vector with the data from the actual guest write request.
* If non-NULL, this is meant to be merged together with the data
const char *name,
Error **errp);
+ssize_t coroutine_fn
+qcow2_co_compress(BlockDriverState *bs, void *dest, size_t dest_size,
+ const void *src, size_t src_size);
+ssize_t coroutine_fn
+qcow2_co_decompress(BlockDriverState *bs, void *dest, size_t dest_size,
+ const void *src, size_t src_size);
+int coroutine_fn
+qcow2_co_encrypt(BlockDriverState *bs, uint64_t file_cluster_offset,
+ uint64_t offset, void *buf, size_t len);
+int coroutine_fn
+qcow2_co_decrypt(BlockDriverState *bs, uint64_t file_cluster_offset,
+ uint64_t offset, void *buf, size_t len);
+
#endif
child = bdrv_attach_child(bs, child_bs, indexstr, &child_format, errp);
if (child == NULL) {
s->next_child_index--;
- bdrv_unref(child_bs);
goto out;
}
s->children = g_renew(BdrvChild *, s->children, s->num_children + 1);
qcow2_writev_data(void *co, uint64_t offset) "co %p offset 0x%" PRIx64
qcow2_pwrite_zeroes_start_req(void *co, int64_t offset, int count) "co %p offset 0x%" PRIx64 " count %d"
qcow2_pwrite_zeroes(void *co, int64_t offset, int count) "co %p offset 0x%" PRIx64 " count %d"
+qcow2_skip_cow(void *co, uint64_t offset, int nb_clusters) "co %p offset 0x%" PRIx64 " nb_clusters %d"
# qcow2-cluster.c
qcow2_alloc_clusters_offset(void *co, uint64_t offset, int bytes) "co %p offset 0x%" PRIx64 " bytes %d"
}
}
-static BdrvDirtyBitmap *do_block_dirty_bitmap_merge(const char *node,
- const char *target,
- strList *bitmaps,
- HBitmap **backup,
- Error **errp);
+static BdrvDirtyBitmap *do_block_dirty_bitmap_merge(
+ const char *node, const char *target,
+ BlockDirtyBitmapMergeSourceList *bitmaps,
+ HBitmap **backup, Error **errp);
static void block_dirty_bitmap_merge_prepare(BlkActionState *common,
Error **errp)
bdrv_disable_dirty_bitmap(bitmap);
}
-static BdrvDirtyBitmap *do_block_dirty_bitmap_merge(const char *node,
- const char *target,
- strList *bitmaps,
- HBitmap **backup,
- Error **errp)
+static BdrvDirtyBitmap *do_block_dirty_bitmap_merge(
+ const char *node, const char *target,
+ BlockDirtyBitmapMergeSourceList *bitmaps,
+ HBitmap **backup, Error **errp)
{
BlockDriverState *bs;
BdrvDirtyBitmap *dst, *src, *anon;
- strList *lst;
+ BlockDirtyBitmapMergeSourceList *lst;
Error *local_err = NULL;
dst = block_dirty_bitmap_lookup(node, target, &bs, errp);
}
for (lst = bitmaps; lst; lst = lst->next) {
- src = bdrv_find_dirty_bitmap(bs, lst->value);
- if (!src) {
- error_setg(errp, "Dirty bitmap '%s' not found", lst->value);
- dst = NULL;
- goto out;
+ switch (lst->value->type) {
+ const char *name, *node;
+ case QTYPE_QSTRING:
+ name = lst->value->u.local;
+ src = bdrv_find_dirty_bitmap(bs, name);
+ if (!src) {
+ error_setg(errp, "Dirty bitmap '%s' not found", name);
+ dst = NULL;
+ goto out;
+ }
+ break;
+ case QTYPE_QDICT:
+ node = lst->value->u.external.node;
+ name = lst->value->u.external.name;
+ src = block_dirty_bitmap_lookup(node, name, NULL, errp);
+ if (!src) {
+ dst = NULL;
+ goto out;
+ }
+ break;
+ default:
+ abort();
}
bdrv_merge_dirty_bitmap(anon, src, NULL, &local_err);
}
void qmp_block_dirty_bitmap_merge(const char *node, const char *target,
- strList *bitmaps, Error **errp)
+ BlockDirtyBitmapMergeSourceList *bitmaps,
+ Error **errp)
{
do_block_dirty_bitmap_merge(node, target, bitmaps, NULL, errp);
}
backup->compress = false;
}
- bs = qmp_get_root_bs(backup->device, errp);
+ bs = bdrv_lookup_bs(backup->device, backup->device, errp);
if (!bs) {
return NULL;
}
+ if (!bs->drv) {
+ error_setg(errp, "Device has no medium");
+ return NULL;
+ }
+
aio_context = bdrv_get_aio_context(bs);
aio_context_acquire(aio_context);
{
BdrvChild *c;
+ bdrv_ref(bs);
c = bdrv_root_attach_child(bs, name, &child_job, perm, shared_perm,
job, errp);
if (c == NULL) {
}
job->nodes = g_slist_prepend(job->nodes, c);
- bdrv_ref(bs);
bdrv_op_block_all(bs, job->blocker);
return 0;
CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
+CONFIG_SEMIHOSTING=y
#
#CONFIG_MILKYMIST_TMU2=n # disabling it actually causes compile-time failures
+CONFIG_SEMIHOSTING=y
+
# Boards:
#
CONFIG_LM32=y
# Default configuration for m68k-softmmu
+CONFIG_SEMIHOSTING=y
+
# Boards:
#
CONFIG_AN5206=y
CONFIG_MIPS_ITU=y
CONFIG_R4K=y
CONFIG_MALTA=y
+CONFIG_SEMIHOSTING=y
CONFIG_PCNET_PCI=y
CONFIG_MIPSSIM=y
CONFIG_ACPI_SMBUS=y
# Default configuration for nios2-softmmu
+CONFIG_SEMIHOSTING=y
+
# Boards:
#
CONFIG_NIOS2_10M50=y
# Default configuration for Xtensa
+CONFIG_SEMIHOSTING=y
+
# Boards:
#
CONFIG_XTENSA_SIM=y
#include "qemu/sockets.h"
#include "sysemu/hw_accel.h"
#include "sysemu/kvm.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "exec/exec-all.h"
#ifdef CONFIG_USER_ONLY
source rdma/Kconfig
source scsi/Kconfig
source sd/Kconfig
+source semihosting/Kconfig
source smbios/Kconfig
source ssi/Kconfig
source timer/Kconfig
devices-dirs-$(CONFIG_SOFTMMU) += xen/
devices-dirs-$(CONFIG_MEM_DEVICE) += mem/
devices-dirs-$(CONFIG_SOFTMMU) += smbios/
+devices-dirs-y += semihosting/
devices-dirs-y += core/
common-obj-y += $(devices-dirs-y)
obj-y += $(devices-dirs-y)
ram_addr_t max_ram_size;
bmc = g_new0(AspeedBoardState, 1);
- object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name);
- object_property_add_child(OBJECT(machine), "soc", OBJECT(&bmc->soc),
- &error_abort);
+ object_initialize_child(OBJECT(machine), "soc", &bmc->soc,
+ (sizeof(bmc->soc)), cfg->soc_name, &error_abort,
+ NULL);
sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int i;
- object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);
- object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
+ object_initialize_child(obj, "cpu", OBJECT(&s->cpu), sizeof(s->cpu),
+ sc->info->cpu_type, &error_abort, NULL);
- object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
- object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
- qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
+ sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
+ TYPE_ASPEED_SCU);
qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
sc->info->silicon_rev);
object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
"hw-prot-key", &error_abort);
- object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
- object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
- qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
+ sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
+ TYPE_ASPEED_VIC);
- object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
- object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
+ sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
+ sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
OBJECT(&s->scu), &error_abort);
- qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
- object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
- object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
- qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
+ sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
+ TYPE_ASPEED_I2C);
- object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);
- object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
- qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
+ sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
+ sc->info->fmc_typename);
object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
&error_abort);
for (i = 0; i < sc->info->spis_num; i++) {
- object_initialize(&s->spi[i], sizeof(s->spi[i]),
- sc->info->spi_typename[i]);
- object_property_add_child(obj, "spi[*]", OBJECT(&s->spi[i]), NULL);
- qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
+ sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
+ sizeof(s->spi[i]), sc->info->spi_typename[i]);
}
- object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
- object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
- qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
+ sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
+ TYPE_ASPEED_SDMC);
qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
sc->info->silicon_rev);
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
"max-ram-size", &error_abort);
for (i = 0; i < sc->info->wdts_num; i++) {
- object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
- object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL);
- qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default());
+ sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
+ sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
sc->info->silicon_rev);
}
- object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
- object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
- qdev_set_parent_bus(DEVICE(&s->ftgmac100), sysbus_get_default());
+ sysbus_init_child_obj(obj, "ftgmac100", OBJECT(&s->ftgmac100),
+ sizeof(s->ftgmac100), TYPE_FTGMAC100);
}
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
MBOX_CHAN_COUNT << MBOX_AS_CHAN_SHIFT);
/* Interrupt Controller */
- object_initialize(&s->ic, sizeof(s->ic), TYPE_BCM2835_IC);
- object_property_add_child(obj, "ic", OBJECT(&s->ic), NULL);
- qdev_set_parent_bus(DEVICE(&s->ic), sysbus_get_default());
+ sysbus_init_child_obj(obj, "ic", &s->ic, sizeof(s->ic), TYPE_BCM2835_IC);
/* UART0 */
- s->uart0 = SYS_BUS_DEVICE(object_new("pl011"));
- object_property_add_child(obj, "uart0", OBJECT(s->uart0), NULL);
- qdev_set_parent_bus(DEVICE(s->uart0), sysbus_get_default());
+ sysbus_init_child_obj(obj, "uart0", &s->uart0, sizeof(s->uart0),
+ TYPE_PL011);
/* AUX / UART1 */
- object_initialize(&s->aux, sizeof(s->aux), TYPE_BCM2835_AUX);
- object_property_add_child(obj, "aux", OBJECT(&s->aux), NULL);
- qdev_set_parent_bus(DEVICE(&s->aux), sysbus_get_default());
+ sysbus_init_child_obj(obj, "aux", &s->aux, sizeof(s->aux),
+ TYPE_BCM2835_AUX);
/* Mailboxes */
- object_initialize(&s->mboxes, sizeof(s->mboxes), TYPE_BCM2835_MBOX);
- object_property_add_child(obj, "mbox", OBJECT(&s->mboxes), NULL);
- qdev_set_parent_bus(DEVICE(&s->mboxes), sysbus_get_default());
+ sysbus_init_child_obj(obj, "mbox", &s->mboxes, sizeof(s->mboxes),
+ TYPE_BCM2835_MBOX);
object_property_add_const_link(OBJECT(&s->mboxes), "mbox-mr",
OBJECT(&s->mbox_mr), &error_abort);
/* Framebuffer */
- object_initialize(&s->fb, sizeof(s->fb), TYPE_BCM2835_FB);
- object_property_add_child(obj, "fb", OBJECT(&s->fb), NULL);
+ sysbus_init_child_obj(obj, "fb", &s->fb, sizeof(s->fb), TYPE_BCM2835_FB);
object_property_add_alias(obj, "vcram-size", OBJECT(&s->fb), "vcram-size",
&error_abort);
- qdev_set_parent_bus(DEVICE(&s->fb), sysbus_get_default());
object_property_add_const_link(OBJECT(&s->fb), "dma-mr",
OBJECT(&s->gpu_bus_mr), &error_abort);
/* Property channel */
- object_initialize(&s->property, sizeof(s->property), TYPE_BCM2835_PROPERTY);
- object_property_add_child(obj, "property", OBJECT(&s->property), NULL);
+ sysbus_init_child_obj(obj, "property", &s->property, sizeof(s->property),
+ TYPE_BCM2835_PROPERTY);
object_property_add_alias(obj, "board-rev", OBJECT(&s->property),
"board-rev", &error_abort);
- qdev_set_parent_bus(DEVICE(&s->property), sysbus_get_default());
object_property_add_const_link(OBJECT(&s->property), "fb",
OBJECT(&s->fb), &error_abort);
OBJECT(&s->gpu_bus_mr), &error_abort);
/* Random Number Generator */
- object_initialize(&s->rng, sizeof(s->rng), TYPE_BCM2835_RNG);
- object_property_add_child(obj, "rng", OBJECT(&s->rng), NULL);
- qdev_set_parent_bus(DEVICE(&s->rng), sysbus_get_default());
+ sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng),
+ TYPE_BCM2835_RNG);
/* Extended Mass Media Controller */
- object_initialize(&s->sdhci, sizeof(s->sdhci), TYPE_SYSBUS_SDHCI);
- object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL);
- qdev_set_parent_bus(DEVICE(&s->sdhci), sysbus_get_default());
+ sysbus_init_child_obj(obj, "sdhci", &s->sdhci, sizeof(s->sdhci),
+ TYPE_SYSBUS_SDHCI);
/* SDHOST */
- object_initialize(&s->sdhost, sizeof(s->sdhost), TYPE_BCM2835_SDHOST);
- object_property_add_child(obj, "sdhost", OBJECT(&s->sdhost), NULL);
- qdev_set_parent_bus(DEVICE(&s->sdhost), sysbus_get_default());
+ sysbus_init_child_obj(obj, "sdhost", &s->sdhost, sizeof(s->sdhost),
+ TYPE_BCM2835_SDHOST);
/* DMA Channels */
- object_initialize(&s->dma, sizeof(s->dma), TYPE_BCM2835_DMA);
- object_property_add_child(obj, "dma", OBJECT(&s->dma), NULL);
- qdev_set_parent_bus(DEVICE(&s->dma), sysbus_get_default());
+ sysbus_init_child_obj(obj, "dma", &s->dma, sizeof(s->dma),
+ TYPE_BCM2835_DMA);
object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
OBJECT(&s->gpu_bus_mr), &error_abort);
/* GPIO */
- object_initialize(&s->gpio, sizeof(s->gpio), TYPE_BCM2835_GPIO);
- object_property_add_child(obj, "gpio", OBJECT(&s->gpio), NULL);
- qdev_set_parent_bus(DEVICE(&s->gpio), sysbus_get_default());
+ sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
+ TYPE_BCM2835_GPIO);
object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci",
OBJECT(&s->sdhci.sdbus), &error_abort);
sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));
/* UART0 */
- qdev_prop_set_chr(DEVICE(s->uart0), "chardev", serial_hd(0));
- object_property_set_bool(OBJECT(s->uart0), true, "realized", &err);
+ qdev_prop_set_chr(DEVICE(&s->uart0), "chardev", serial_hd(0));
+ object_property_set_bool(OBJECT(&s->uart0), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->peri_mr, UART0_OFFSET,
- sysbus_mmio_get_region(s->uart0, 0));
- sysbus_connect_irq(s->uart0, 0,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart0), 0));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart0), 0,
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
INTERRUPT_UART));
/* AUX / UART1 */
static void digic_init(Object *obj)
{
DigicState *s = DIGIC(obj);
- DeviceState *dev;
int i;
- object_initialize(&s->cpu, sizeof(s->cpu), "arm946-" TYPE_ARM_CPU);
- object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
+ object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
+ "arm946-" TYPE_ARM_CPU, &error_abort, NULL);
for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
#define DIGIC_TIMER_NAME_MLEN 11
char name[DIGIC_TIMER_NAME_MLEN];
- object_initialize(&s->timer[i], sizeof(s->timer[i]), TYPE_DIGIC_TIMER);
- dev = DEVICE(&s->timer[i]);
- qdev_set_parent_bus(dev, sysbus_get_default());
snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i);
- object_property_add_child(obj, name, OBJECT(&s->timer[i]), NULL);
+ sysbus_init_child_obj(obj, name, &s->timer[i], sizeof(s->timer[i]),
+ TYPE_DIGIC_TIMER);
}
- object_initialize(&s->uart, sizeof(s->uart), TYPE_DIGIC_UART);
- dev = DEVICE(&s->uart);
- qdev_set_parent_bus(dev, sysbus_get_default());
- object_property_add_child(obj, "uart", OBJECT(&s->uart), NULL);
+ sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
+ TYPE_DIGIC_UART);
}
static void digic_realize(DeviceState *dev, Error **errp)
unsigned int alias_offset;
int i;
- object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX25);
- object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
- &error_abort);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
+ TYPE_FSL_IMX25, &error_abort, NULL);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
unsigned int alias_offset;
unsigned int i;
- object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX31);
- object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
- &error_abort);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
+ TYPE_FSL_IMX31, &error_abort, NULL);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
DeviceState *sccdev;
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
- object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC);
+ sysbus_init_child_obj(OBJECT(mms), "scc", scc,
+ sizeof(mms->scc), TYPE_MPS2_SCC);
sccdev = DEVICE(scc);
- qdev_set_parent_bus(sccdev, sysbus_get_default());
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
{
MPS2FPGAIO *fpgaio = opaque;
- object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO);
- qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default());
+ sysbus_init_child_obj(OBJECT(mms), "fpgaio", fpgaio,
+ sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO);
object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0);
}
g_assert_not_reached();
}
- object_initialize(&mms->armv7m, sizeof(mms->armv7m), TYPE_ARMV7M);
+ sysbus_init_child_obj(OBJECT(mms), "armv7m", &mms->armv7m,
+ sizeof(mms->armv7m), TYPE_ARMV7M);
armv7m = DEVICE(&mms->armv7m);
- qdev_set_parent_bus(armv7m, sysbus_get_default());
switch (mmc->fpga_type) {
case FPGA_AN385:
qdev_prop_set_uint32(armv7m, "num-irq", 32);
qdev_get_gpio_in(armv7m, 10));
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
- object_initialize(&mms->scc, sizeof(mms->scc), TYPE_MPS2_SCC);
+ sysbus_init_child_obj(OBJECT(mms), "scc", &mms->scc,
+ sizeof(mms->scc), TYPE_MPS2_SCC);
sccdev = DEVICE(&mms->scc);
- qdev_set_parent_bus(sccdev, sysbus_get_default());
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
exit(1);
}
- object_initialize(&s->soc, sizeof(s->soc),
- version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
- object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
- &error_abort);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
+ version == 3 ? TYPE_BCM2837 : TYPE_BCM2836,
+ &error_abort, NULL);
/* Allocate and map RAM */
memory_region_allocate_system_memory(&s->ram, OBJECT(machine), "ram",
exit(1);
}
- object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX6);
- object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
- &error_abort);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
+ TYPE_FSL_IMX6, &error_abort, NULL);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &err);
if (err != NULL) {
memory_region_allocate_system_memory(&s->ddr_ram, NULL, "ddr-ram",
ram_size);
- object_initialize(&s->soc, sizeof(s->soc), TYPE_XLNX_ZYNQMP);
- object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
- &error_abort);
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
+ TYPE_XLNX_ZYNQMP, &error_abort, NULL);
object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram),
"ddr-ram", &error_abort);
for (i = 0; i < num_rpus; i++) {
char *name;
- object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
- "cortex-r5f-" TYPE_ARM_CPU);
- object_property_add_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
- OBJECT(&s->rpu_cpu[i]), &error_abort);
+ object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
+ &s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
+ "cortex-r5f-" TYPE_ARM_CPU, &error_abort,
+ NULL);
name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
if (strcmp(name, boot_cpu)) {
* as we didn't know then if the CPU had the security extensions;
* so we have to do it here.
*/
- object_initialize(&s->systick[M_REG_S], sizeof(s->systick[M_REG_S]),
- TYPE_SYSTICK);
- qdev_set_parent_bus(DEVICE(&s->systick[M_REG_S]), sysbus_get_default());
+ sysbus_init_child_obj(OBJECT(dev), "systick-reg-s",
+ &s->systick[M_REG_S],
+ sizeof(s->systick[M_REG_S]), TYPE_SYSTICK);
object_property_set_bool(OBJECT(&s->systick[M_REG_S]), true,
"realized", &err);
/*< public >*/
MicroBlazeCPU cpu;
XlnxPMUIOIntc intc;
+ XlnxZynqMPIPI ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
} XlnxZynqMPPMUSoCState;
sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
TYPE_XLNX_PMU_IO_INTC);
+
+ /* Create the IPI device */
+ for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
+ char *name = g_strdup_printf("ipi%d", i);
+ sysbus_init_child_obj(obj, name, &s->ipi[i],
+ sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);
+ g_free(name);
+ }
}
static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->intc), 0, XLNX_ZYNQMP_PMU_INTC_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->intc), 0,
qdev_get_gpio_in(DEVICE(&s->cpu), MB_CPU_IRQ));
+
+ /* Connect the IPI device */
+ for (int i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
+ object_property_set_bool(OBJECT(&s->ipi[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ipi[i]), 0, ipi_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ipi[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->intc), ipi_irq[i]));
+ }
}
static void xlnx_zynqmp_pmu_soc_class_init(ObjectClass *oc, void *data)
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
- XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
- qemu_irq irq[32];
- int i;
/* Create the ROM */
memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom",
pmu_ram);
/* Create the PMU device */
- object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC);
- object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu),
- &error_abort);
+ object_initialize_child(OBJECT(machine), "pmu", pmu,
+ sizeof(XlnxZynqMPPMUSoCState),
+ TYPE_XLNX_ZYNQMP_PMU_SOC, &error_abort, NULL);
object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal);
- for (i = 0; i < 32; i++) {
- irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i);
- }
-
- /* Create and connect the IPI device */
- for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
- ipi[i] = g_new0(XlnxZynqMPIPI, 1);
- object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI);
- qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default());
- }
-
- for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) {
- object_property_set_bool(OBJECT(ipi[i]), true, "realized",
- &error_abort);
- sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]);
- sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
- }
-
/* Load the kernel */
microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
machine->ram_size,
SysBusDevice parent_obj;
MachineState *mach;
- MIPSCPSState *cps;
+ MIPSCPSState cps;
SerialState *uart;
CharBackend lcd_display;
case PLAT_DDR3_STATUS:
return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED;
case PLAT_MMCM_DIV:
- gic_freq = mips_gictimer_get_freq(s->cps->gic.gic_timer) / 1000000;
+ gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000;
val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT;
val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT;
val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT;
is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
- s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
- qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
-
- object_property_set_str(OBJECT(s->cps), machine->cpu_type, "cpu-type",
+ sysbus_init_child_obj(OBJECT(machine), "cps", OBJECT(&s->cps),
+ sizeof(s->cps), TYPE_MIPS_CPS);
+ object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type",
&err);
- object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
- object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
+ object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err);
+ object_property_set_bool(OBJECT(&s->cps), true, "realized", &err);
if (err != NULL) {
error_report("%s", error_get_pretty(err));
exit(1);
}
- sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
flash = g_new(MemoryRegion, 1);
memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err);
xilinx_pcie_init(sys_mem, 0,
0x10000000, 32 * MiB,
0x40000000, 1 * GiB,
- get_cps_irq(s->cps, 2), false);
+ get_cps_irq(&s->cps, 2), false);
xilinx_pcie_init(sys_mem, 1,
0x12000000, 32 * MiB,
0x20000000, 512 * MiB,
- get_cps_irq(s->cps, 1), false);
+ get_cps_irq(&s->cps, 1), false);
pcie2 = xilinx_pcie_init(sys_mem, 2,
0x14000000, 32 * MiB,
0x16000000, 1 * MiB,
- get_cps_irq(s->cps, 0), true);
+ get_cps_irq(&s->cps, 0), true);
platreg = g_new(MemoryRegion, 1);
memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0);
s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
- get_cps_irq(s->cps, 3), 10000000,
+ get_cps_irq(&s->cps, 3), 10000000,
serial_hd(0), DEVICE_NATIVE_ENDIAN);
lcd = g_new(MemoryRegion, 1);
/* Inter-Thread Communication Unit */
if (itu_present) {
- object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU);
- qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default());
-
+ sysbus_init_child_obj(OBJECT(dev), "itu", &s->itu, sizeof(s->itu),
+ TYPE_MIPS_ITU);
object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present",
}
/* Cluster Power Controller */
- object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
- qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
-
+ sysbus_init_child_obj(OBJECT(dev), "cpc", &s->cpc, sizeof(s->cpc),
+ TYPE_MIPS_CPC);
object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err);
object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err);
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
/* Global Interrupt Controller */
- object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC);
- qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
-
+ sysbus_init_child_obj(OBJECT(dev), "gic", &s->gic, sizeof(s->gic),
+ TYPE_MIPS_GIC);
object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err);
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
/* Global Configuration Registers */
gcr_base = env->CP0_CMGCRBase << 4;
- object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR);
- qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default());
-
+ sysbus_init_child_obj(OBJECT(dev), "gcr", &s->gcr, sizeof(s->gcr),
+ TYPE_MIPS_GCR);
object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
#include "qemu/error-report.h"
#include "hw/empty_slot.h"
#include "sysemu/kvm.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "hw/mips/cps.h"
#define ENVP_ADDR 0x80002000l
typedef struct {
SysBusDevice parent_obj;
- MIPSCPSState *cps;
+ MIPSCPSState cps;
qemu_irq *i8259;
} MaltaState;
{
Error *err = NULL;
- s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
- qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
-
- object_property_set_str(OBJECT(s->cps), cpu_type, "cpu-type", &err);
- object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
- object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
+ sysbus_init_child_obj(OBJECT(s), "cps", OBJECT(&s->cps), sizeof(s->cps),
+ TYPE_MIPS_CPS);
+ object_property_set_str(OBJECT(&s->cps), cpu_type, "cpu-type", &err);
+ object_property_set_int(OBJECT(&s->cps), smp_cpus, "num-vp", &err);
+ object_property_set_bool(OBJECT(&s->cps), true, "realized", &err);
if (err != NULL) {
error_report("%s", error_get_pretty(err));
exit(1);
}
- sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1);
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
- *i8259_irq = get_cps_irq(s->cps, 3);
+ *i8259_irq = get_cps_irq(&s->cps, 3);
*cbus_irq = NULL;
}
object_property_set_bool(OBJECT(&ns->gpio), true, "realized", &err);
/* PMU */
- object_initialize(&s->pmu, sizeof(s->pmu), TYPE_VIA_PMU);
+ object_initialize_child(OBJECT(s), "pmu", &s->pmu, sizeof(s->pmu),
+ TYPE_VIA_PMU, &error_abort, NULL);
object_property_set_link(OBJECT(&s->pmu), OBJECT(sysbus_dev), "gpio",
&error_abort);
qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb);
qdev_set_parent_bus(DEVICE(&s->pmu), BUS(&s->macio_bus));
- object_property_add_child(OBJECT(s), "pmu", OBJECT(&s->pmu), NULL);
object_property_set_bool(OBJECT(&s->pmu), true, "realized", &err);
if (err) {
sysbus_mmio_get_region(sysbus_dev, 0));
} else {
/* CUDA */
- object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA);
+ object_initialize_child(OBJECT(s), "cuda", &s->cuda, sizeof(s->cuda),
+ TYPE_CUDA, &error_abort, NULL);
qdev_set_parent_bus(DEVICE(&s->cuda), BUS(&s->macio_bus));
- object_property_add_child(OBJECT(s), "cuda", OBJECT(&s->cuda), NULL);
qdev_prop_set_uint64(DEVICE(&s->cuda), "timebase-frequency",
s->frequency);
PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize);
int core_id = CPU_CORE(pnv_core)->core_id;
- object_initialize(eq, sizeof(*eq), TYPE_PNV_QUAD);
snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
+ object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq),
+ TYPE_PNV_QUAD, &error_fatal, NULL);
- object_property_add_child(OBJECT(chip), eq_name, OBJECT(eq),
- &error_fatal);
object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal);
object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal);
- object_unref(OBJECT(eq));
pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
&eq->xscom_regs);
continue;
}
- object_initialize(pnv_core, typesize, typename);
snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
- object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
- &error_fatal);
+ object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize,
+ typename, &error_fatal, NULL);
object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
&error_fatal);
object_property_set_int(OBJECT(pnv_core), core_hwid,
OBJECT(chip), &error_fatal);
object_property_set_bool(OBJECT(pnv_core), true, "realized",
&error_fatal);
- object_unref(OBJECT(pnv_core));
/* Each core has an XSCOM MMIO region */
if (!pnv_chip_is_power9(chip)) {
obj-$(CONFIG_HART) += riscv_hart.o
obj-$(CONFIG_SIFIVE_E) += sifive_e.o
obj-$(CONFIG_SIFIVE) += sifive_clint.o
+obj-$(CONFIG_SIFIVE) += sifive_gpio.o
obj-$(CONFIG_SIFIVE) += sifive_prci.o
obj-$(CONFIG_SIFIVE) += sifive_plic.o
obj-$(CONFIG_SIFIVE) += sifive_test.o
&error_abort);
object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
&error_abort);
+ sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0",
+ &s->gpio, sizeof(s->gpio),
+ TYPE_SIFIVE_GPIO);
}
static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
{
const struct MemmapEntry *memmap = sifive_e_memmap;
+ Error *err = NULL;
SiFiveESoCState *s = RISCV_E_SOC(dev);
MemoryRegion *sys_mem = get_system_memory();
sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
- sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0",
- memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size);
+
+ /* GPIO */
+
+ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ /* Map GPIO registers */
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
+
+ /* Pass all GPIOs to the SOC layer so they are available to the board */
+ qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
+
+ /* Connect GPIO interrupts to the PLIC */
+ for (int i = 0; i < 32; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
+ qdev_get_gpio_in(DEVICE(s->plic),
+ SIFIVE_E_GPIO0_IRQ0 + i));
+ }
+
sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
--- /dev/null
+/*
+ * sifive System-on-Chip general purpose input/output register definition
+ *
+ * Copyright 2019 AdaCore
+ *
+ * Base on nrf51_gpio.c:
+ *
+ * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/riscv/sifive_gpio.h"
+#include "trace.h"
+
+static void update_output_irq(SIFIVEGPIOState *s)
+{
+
+ uint32_t pending;
+ uint32_t pin;
+
+ pending = s->high_ip & s->high_ie;
+ pending |= s->low_ip & s->low_ie;
+ pending |= s->rise_ip & s->rise_ie;
+ pending |= s->fall_ip & s->fall_ie;
+
+ for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
+ pin = 1 << i;
+ qemu_set_irq(s->irq[i], (pending & pin) != 0);
+ trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0);
+ }
+}
+
+static void update_state(SIFIVEGPIOState *s)
+{
+ size_t i;
+ bool prev_ival, in, in_mask, port, out_xor, pull, output_en, input_en,
+ rise_ip, fall_ip, low_ip, high_ip, oval, actual_value, ival;
+
+ for (i = 0; i < SIFIVE_GPIO_PINS; i++) {
+
+ prev_ival = extract32(s->value, i, 1);
+ in = extract32(s->in, i, 1);
+ in_mask = extract32(s->in_mask, i, 1);
+ port = extract32(s->port, i, 1);
+ out_xor = extract32(s->out_xor, i, 1);
+ pull = extract32(s->pue, i, 1);
+ output_en = extract32(s->output_en, i, 1);
+ input_en = extract32(s->input_en, i, 1);
+ rise_ip = extract32(s->rise_ip, i, 1);
+ fall_ip = extract32(s->fall_ip, i, 1);
+ low_ip = extract32(s->low_ip, i, 1);
+ high_ip = extract32(s->high_ip, i, 1);
+
+ /* Output value (IOF not supported) */
+ oval = output_en && (port ^ out_xor);
+
+ /* Pin both driven externally and internally */
+ if (output_en && in_mask) {
+ qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i);
+ }
+
+ if (in_mask) {
+ /* The pin is driven by external device */
+ actual_value = in;
+ } else if (output_en) {
+ /* The pin is driven by internal circuit */
+ actual_value = oval;
+ } else {
+ /* Floating? Apply pull-up resistor */
+ actual_value = pull;
+ }
+
+ qemu_set_irq(s->output[i], actual_value);
+
+ /* Input value */
+ ival = input_en && actual_value;
+
+ /* Interrupts */
+ high_ip = high_ip || ival;
+ s->high_ip = deposit32(s->high_ip, i, 1, high_ip);
+
+ low_ip = low_ip || !ival;
+ s->low_ip = deposit32(s->low_ip, i, 1, low_ip);
+
+ rise_ip = rise_ip || (ival && !prev_ival);
+ s->rise_ip = deposit32(s->rise_ip, i, 1, rise_ip);
+
+ fall_ip = fall_ip || (!ival && prev_ival);
+ s->fall_ip = deposit32(s->fall_ip, i, 1, fall_ip);
+
+ /* Update value */
+ s->value = deposit32(s->value, i, 1, ival);
+ }
+ update_output_irq(s);
+}
+
+static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size)
+{
+ SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
+ uint64_t r = 0;
+
+ switch (offset) {
+ case SIFIVE_GPIO_REG_VALUE:
+ r = s->value;
+ break;
+
+ case SIFIVE_GPIO_REG_INPUT_EN:
+ r = s->input_en;
+ break;
+
+ case SIFIVE_GPIO_REG_OUTPUT_EN:
+ r = s->output_en;
+ break;
+
+ case SIFIVE_GPIO_REG_PORT:
+ r = s->port;
+ break;
+
+ case SIFIVE_GPIO_REG_PUE:
+ r = s->pue;
+ break;
+
+ case SIFIVE_GPIO_REG_DS:
+ r = s->ds;
+ break;
+
+ case SIFIVE_GPIO_REG_RISE_IE:
+ r = s->rise_ie;
+ break;
+
+ case SIFIVE_GPIO_REG_RISE_IP:
+ r = s->rise_ip;
+ break;
+
+ case SIFIVE_GPIO_REG_FALL_IE:
+ r = s->fall_ie;
+ break;
+
+ case SIFIVE_GPIO_REG_FALL_IP:
+ r = s->fall_ip;
+ break;
+
+ case SIFIVE_GPIO_REG_HIGH_IE:
+ r = s->high_ie;
+ break;
+
+ case SIFIVE_GPIO_REG_HIGH_IP:
+ r = s->high_ip;
+ break;
+
+ case SIFIVE_GPIO_REG_LOW_IE:
+ r = s->low_ie;
+ break;
+
+ case SIFIVE_GPIO_REG_LOW_IP:
+ r = s->low_ip;
+ break;
+
+ case SIFIVE_GPIO_REG_IOF_EN:
+ r = s->iof_en;
+ break;
+
+ case SIFIVE_GPIO_REG_IOF_SEL:
+ r = s->iof_sel;
+ break;
+
+ case SIFIVE_GPIO_REG_OUT_XOR:
+ r = s->out_xor;
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: bad read offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ }
+
+ trace_sifive_gpio_read(offset, r);
+
+ return r;
+}
+
+static void sifive_gpio_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned int size)
+{
+ SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
+
+ trace_sifive_gpio_write(offset, value);
+
+ switch (offset) {
+
+ case SIFIVE_GPIO_REG_INPUT_EN:
+ s->input_en = value;
+ break;
+
+ case SIFIVE_GPIO_REG_OUTPUT_EN:
+ s->output_en = value;
+ break;
+
+ case SIFIVE_GPIO_REG_PORT:
+ s->port = value;
+ break;
+
+ case SIFIVE_GPIO_REG_PUE:
+ s->pue = value;
+ break;
+
+ case SIFIVE_GPIO_REG_DS:
+ s->ds = value;
+ break;
+
+ case SIFIVE_GPIO_REG_RISE_IE:
+ s->rise_ie = value;
+ break;
+
+ case SIFIVE_GPIO_REG_RISE_IP:
+ /* Write 1 to clear */
+ s->rise_ip &= ~value;
+ break;
+
+ case SIFIVE_GPIO_REG_FALL_IE:
+ s->fall_ie = value;
+ break;
+
+ case SIFIVE_GPIO_REG_FALL_IP:
+ /* Write 1 to clear */
+ s->fall_ip &= ~value;
+ break;
+
+ case SIFIVE_GPIO_REG_HIGH_IE:
+ s->high_ie = value;
+ break;
+
+ case SIFIVE_GPIO_REG_HIGH_IP:
+ /* Write 1 to clear */
+ s->high_ip &= ~value;
+ break;
+
+ case SIFIVE_GPIO_REG_LOW_IE:
+ s->low_ie = value;
+ break;
+
+ case SIFIVE_GPIO_REG_LOW_IP:
+ /* Write 1 to clear */
+ s->low_ip &= ~value;
+ break;
+
+ case SIFIVE_GPIO_REG_IOF_EN:
+ s->iof_en = value;
+ break;
+
+ case SIFIVE_GPIO_REG_IOF_SEL:
+ s->iof_sel = value;
+ break;
+
+ case SIFIVE_GPIO_REG_OUT_XOR:
+ s->out_xor = value;
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: bad write offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ }
+
+ update_state(s);
+}
+
+static const MemoryRegionOps gpio_ops = {
+ .read = sifive_gpio_read,
+ .write = sifive_gpio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+};
+
+static void sifive_gpio_set(void *opaque, int line, int value)
+{
+ SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
+
+ trace_sifive_gpio_set(line, value);
+
+ assert(line >= 0 && line < SIFIVE_GPIO_PINS);
+
+ s->in_mask = deposit32(s->in_mask, line, 1, value >= 0);
+ if (value >= 0) {
+ s->in = deposit32(s->in, line, 1, value != 0);
+ }
+
+ update_state(s);
+}
+
+static void sifive_gpio_reset(DeviceState *dev)
+{
+ SIFIVEGPIOState *s = SIFIVE_GPIO(dev);
+
+ s->value = 0;
+ s->input_en = 0;
+ s->output_en = 0;
+ s->port = 0;
+ s->pue = 0;
+ s->ds = 0;
+ s->rise_ie = 0;
+ s->rise_ip = 0;
+ s->fall_ie = 0;
+ s->fall_ip = 0;
+ s->high_ie = 0;
+ s->high_ip = 0;
+ s->low_ie = 0;
+ s->low_ip = 0;
+ s->iof_en = 0;
+ s->iof_sel = 0;
+ s->out_xor = 0;
+ s->in = 0;
+ s->in_mask = 0;
+
+}
+
+static const VMStateDescription vmstate_sifive_gpio = {
+ .name = TYPE_SIFIVE_GPIO,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(value, SIFIVEGPIOState),
+ VMSTATE_UINT32(input_en, SIFIVEGPIOState),
+ VMSTATE_UINT32(output_en, SIFIVEGPIOState),
+ VMSTATE_UINT32(port, SIFIVEGPIOState),
+ VMSTATE_UINT32(pue, SIFIVEGPIOState),
+ VMSTATE_UINT32(rise_ie, SIFIVEGPIOState),
+ VMSTATE_UINT32(rise_ip, SIFIVEGPIOState),
+ VMSTATE_UINT32(fall_ie, SIFIVEGPIOState),
+ VMSTATE_UINT32(fall_ip, SIFIVEGPIOState),
+ VMSTATE_UINT32(high_ie, SIFIVEGPIOState),
+ VMSTATE_UINT32(high_ip, SIFIVEGPIOState),
+ VMSTATE_UINT32(low_ie, SIFIVEGPIOState),
+ VMSTATE_UINT32(low_ip, SIFIVEGPIOState),
+ VMSTATE_UINT32(iof_en, SIFIVEGPIOState),
+ VMSTATE_UINT32(iof_sel, SIFIVEGPIOState),
+ VMSTATE_UINT32(out_xor, SIFIVEGPIOState),
+ VMSTATE_UINT32(in, SIFIVEGPIOState),
+ VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void sifive_gpio_init(Object *obj)
+{
+ SIFIVEGPIOState *s = SIFIVE_GPIO(obj);
+
+ memory_region_init_io(&s->mmio, obj, &gpio_ops, s,
+ TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+
+ for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
+ }
+
+ qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, SIFIVE_GPIO_PINS);
+ qdev_init_gpio_out(DEVICE(s), s->output, SIFIVE_GPIO_PINS);
+}
+
+static void sifive_gpio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_sifive_gpio;
+ dc->reset = sifive_gpio_reset;
+ dc->desc = "sifive GPIO";
+}
+
+static const TypeInfo sifive_gpio_info = {
+ .name = TYPE_SIFIVE_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SIFIVEGPIOState),
+ .instance_init = sifive_gpio_init,
+ .class_init = sifive_gpio_class_init
+};
+
+static void sifive_gpio_register_types(void)
+{
+ type_register_static(&sifive_gpio_info);
+}
+
+type_init(sifive_gpio_register_types)
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
+#include "sysemu/qtest.h"
#include "exec/address-spaces.h"
#include "elf.h"
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
- }
+}
+
+static void spike_board_init(MachineState *machine)
+{
+ const struct MemmapEntry *memmap = spike_memmap;
+
+ SpikeState *s = g_new0(SpikeState, 1);
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+ MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+ int i;
+
+ /* Initialize SOC */
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
+ TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
+ object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
+ &error_abort);
+ object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
+ &error_abort);
+ object_property_set_bool(OBJECT(&s->soc), true, "realized",
+ &error_abort);
+
+ /* register system main memory (actual RAM) */
+ memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
+ machine->ram_size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
+ main_mem);
+
+ /* create device tree */
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+
+ /* boot rom */
+ memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
+ memmap[SPIKE_MROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
+ mask_rom);
+
+ if (machine->kernel_filename) {
+ load_kernel(machine->kernel_filename);
+ }
+
+ /* reset vector */
+ uint32_t reset_vec[8] = {
+ 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
+ 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
+ 0xf1402573, /* csrr a0, mhartid */
+#if defined(TARGET_RISCV32)
+ 0x0182a283, /* lw t0, 24(t0) */
+#elif defined(TARGET_RISCV64)
+ 0x0182b283, /* ld t0, 24(t0) */
+#endif
+ 0x00028067, /* jr t0 */
+ 0x00000000,
+ memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
+ 0x00000000,
+ /* dtb: */
+ };
+
+ /* copy in the reset vector in little_endian byte order */
+ for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
+ reset_vec[i] = cpu_to_le32(reset_vec[i]);
+ }
+ rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
+ memmap[SPIKE_MROM].base, &address_space_memory);
+
+ /* copy in the device tree */
+ if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
+ memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
+ error_report("not enough space to store device-tree");
+ exit(1);
+ }
+ qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
+ rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
+ memmap[SPIKE_MROM].base + sizeof(reset_vec),
+ &address_space_memory);
+
+ /* initialize HTIF using symbols found in load_kernel */
+ htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
+
+ /* Core Local Interruptor (timer and IPI) */
+ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
+ smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
+}
static void spike_v1_10_0_board_init(MachineState *machine)
{
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
int i;
+ if (!qtest_enabled()) {
+ info_report("The Spike v1.10.0 machine has been deprecated. "
+ "Please use the generic spike machine and specify the ISA "
+ "versions using -cpu.");
+ }
+
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
int i;
+ if (!qtest_enabled()) {
+ info_report("The Spike v1.09.1 machine has been deprecated. "
+ "Please use the generic spike machine and specify the ISA "
+ "versions using -cpu.");
+ }
+
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
mc->init = spike_v1_10_0_board_init;
mc->max_cpus = 1;
+}
+
+static void spike_machine_init(MachineClass *mc)
+{
+ mc->desc = "RISC-V Spike Board";
+ mc->init = spike_board_init;
+ mc->max_cpus = 1;
mc->is_default = 1;
+ mc->default_cpu_type = SPIKE_V1_10_0_CPU;
}
DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
+DEFINE_MACHINE("spike", spike_machine_init)
--- /dev/null
+# See docs/devel/tracing.txt for syntax documentation.
+
+# hw/gpio/sifive_gpio.c
+sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
+sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
+sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
+sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
-#include "hw/riscv/riscv_htif.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
/* Initialize SOC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
- object_property_set_str(OBJECT(&s->soc), VIRT_CPU, "cpu-type",
+ object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
&error_abort);
mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
mc->init = riscv_virt_board_init;
mc->max_cpus = 8; /* hardcoded limit in BBL */
+ mc->default_cpu_type = VIRT_CPU;
}
DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
--- /dev/null
+
+config SEMIHOSTING
+ bool
--- /dev/null
+obj-$(CONFIG_SEMIHOSTING) += config.o
+obj-$(CONFIG_SEMIHOSTING) += console.o
--- /dev/null
+/*
+ * Semihosting configuration
+ *
+ * Copyright (c) 2015 Imagination Technologies
+ * Copyright (c) 2019 Linaro Ltd
+ *
+ * This controls the configuration of semihosting for all guest
+ * targets that support it. Architecture specific handling is handled
+ * in target/HW/HW-semi.c
+ *
+ * Semihosting is sightly strange in that it is also supported by some
+ * linux-user targets. However in that use case no configuration of
+ * the outputs and command lines is supported.
+ *
+ * The config module is common to all softmmu targets however as vl.c
+ * needs to link against the helpers.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/option.h"
+#include "qemu/config-file.h"
+#include "qemu/error-report.h"
+#include "hw/semihosting/semihost.h"
+#include "chardev/char.h"
+
+QemuOptsList qemu_semihosting_config_opts = {
+ .name = "semihosting-config",
+ .implied_opt_name = "enable",
+ .head = QTAILQ_HEAD_INITIALIZER(qemu_semihosting_config_opts.head),
+ .desc = {
+ {
+ .name = "enable",
+ .type = QEMU_OPT_BOOL,
+ }, {
+ .name = "target",
+ .type = QEMU_OPT_STRING,
+ }, {
+ .name = "chardev",
+ .type = QEMU_OPT_STRING,
+ }, {
+ .name = "arg",
+ .type = QEMU_OPT_STRING,
+ },
+ { /* end of list */ }
+ },
+};
+
+typedef struct SemihostingConfig {
+ bool enabled;
+ SemihostingTarget target;
+ Chardev *chardev;
+ const char **argv;
+ int argc;
+ const char *cmdline; /* concatenated argv */
+} SemihostingConfig;
+
+static SemihostingConfig semihosting;
+static const char *semihost_chardev;
+
+bool semihosting_enabled(void)
+{
+ return semihosting.enabled;
+}
+
+SemihostingTarget semihosting_get_target(void)
+{
+ return semihosting.target;
+}
+
+const char *semihosting_get_arg(int i)
+{
+ if (i >= semihosting.argc) {
+ return NULL;
+ }
+ return semihosting.argv[i];
+}
+
+int semihosting_get_argc(void)
+{
+ return semihosting.argc;
+}
+
+const char *semihosting_get_cmdline(void)
+{
+ if (semihosting.cmdline == NULL && semihosting.argc > 0) {
+ semihosting.cmdline = g_strjoinv(" ", (gchar **)semihosting.argv);
+ }
+ return semihosting.cmdline;
+}
+
+static int add_semihosting_arg(void *opaque,
+ const char *name, const char *val,
+ Error **errp)
+{
+ SemihostingConfig *s = opaque;
+ if (strcmp(name, "arg") == 0) {
+ s->argc++;
+ /* one extra element as g_strjoinv() expects NULL-terminated array */
+ s->argv = g_realloc(s->argv, (s->argc + 1) * sizeof(void *));
+ s->argv[s->argc - 1] = val;
+ s->argv[s->argc] = NULL;
+ }
+ return 0;
+}
+
+/* Use strings passed via -kernel/-append to initialize semihosting.argv[] */
+void semihosting_arg_fallback(const char *file, const char *cmd)
+{
+ char *cmd_token;
+
+ /* argv[0] */
+ add_semihosting_arg(&semihosting, "arg", file, NULL);
+
+ /* split -append and initialize argv[1..n] */
+ cmd_token = strtok(g_strdup(cmd), " ");
+ while (cmd_token) {
+ add_semihosting_arg(&semihosting, "arg", cmd_token, NULL);
+ cmd_token = strtok(NULL, " ");
+ }
+}
+
+Chardev *semihosting_get_chardev(void)
+{
+ return semihosting.chardev;
+}
+
+void qemu_semihosting_enable(void)
+{
+ semihosting.enabled = true;
+ semihosting.target = SEMIHOSTING_TARGET_AUTO;
+}
+
+int qemu_semihosting_config_options(const char *optarg)
+{
+ QemuOptsList *opt_list = qemu_find_opts("semihosting-config");
+ QemuOpts *opts = qemu_opts_parse_noisily(opt_list, optarg, false);
+
+ semihosting.enabled = true;
+
+ if (opts != NULL) {
+ semihosting.enabled = qemu_opt_get_bool(opts, "enable",
+ true);
+ const char *target = qemu_opt_get(opts, "target");
+ /* setup of chardev is deferred until they are initialised */
+ semihost_chardev = qemu_opt_get(opts, "chardev");
+ if (target != NULL) {
+ if (strcmp("native", target) == 0) {
+ semihosting.target = SEMIHOSTING_TARGET_NATIVE;
+ } else if (strcmp("gdb", target) == 0) {
+ semihosting.target = SEMIHOSTING_TARGET_GDB;
+ } else if (strcmp("auto", target) == 0) {
+ semihosting.target = SEMIHOSTING_TARGET_AUTO;
+ } else {
+ error_report("unsupported semihosting-config %s",
+ optarg);
+ return 1;
+ }
+ } else {
+ semihosting.target = SEMIHOSTING_TARGET_AUTO;
+ }
+ /* Set semihosting argument count and vector */
+ qemu_opt_foreach(opts, add_semihosting_arg,
+ &semihosting, NULL);
+ } else {
+ error_report("unsupported semihosting-config %s", optarg);
+ return 1;
+ }
+
+ return 0;
+}
+
+void qemu_semihosting_connect_chardevs(void)
+{
+ /* We had to defer this until chardevs were created */
+ if (semihost_chardev) {
+ Chardev *chr = qemu_chr_find(semihost_chardev);
+ if (chr == NULL) {
+ error_report("semihosting chardev '%s' not found",
+ semihost_chardev);
+ exit(1);
+ }
+ semihosting.chardev = chr;
+ }
+}
--- /dev/null
+/*
+ * Semihosting Console Support
+ *
+ * Copyright (c) 2015 Imagination Technologies
+ * Copyright (c) 2019 Linaro Ltd
+ *
+ * This provides support for outputting to a semihosting console.
+ *
+ * While most semihosting implementations support reading and writing
+ * to arbitrary file descriptors we treat the console as something
+ * specifically for debugging interaction. This means messages can be
+ * re-directed to gdb (if currently being used to debug) or even
+ * re-directed elsewhere.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "hw/semihosting/semihost.h"
+#include "hw/semihosting/console.h"
+#include "exec/gdbstub.h"
+#include "qemu/log.h"
+#include "chardev/char.h"
+
+int qemu_semihosting_log_out(const char *s, int len)
+{
+ Chardev *chardev = semihosting_get_chardev();
+ if (chardev) {
+ return qemu_chr_write_all(chardev, (uint8_t *) s, len);
+ } else {
+ return write(STDERR_FILENO, s, len);
+ }
+}
+
+/*
+ * A re-implementation of lock_user_string that we can use locally
+ * instead of relying on softmmu-semi. Hopefully we can deprecate that
+ * in time. We either copy len bytes if specified or until we find a NULL.
+ */
+static GString *copy_user_string(CPUArchState *env, target_ulong addr, int len)
+{
+ CPUState *cpu = ENV_GET_CPU(env);
+ GString *s = g_string_sized_new(len ? len : 128);
+ uint8_t c;
+ bool done;
+
+ do {
+ if (cpu_memory_rw_debug(cpu, addr++, &c, 1, 0) == 0) {
+ s = g_string_append_c(s, c);
+ done = len ? s->len == len : c == 0;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: passed inaccessible address " TARGET_FMT_lx,
+ __func__, addr);
+ done = true;
+ }
+ } while (!done);
+
+ return s;
+}
+
+static void semihosting_cb(CPUState *cs, target_ulong ret, target_ulong err)
+{
+ if (ret == (target_ulong) -1) {
+ qemu_log("%s: gdb console output failed ("TARGET_FMT_ld")",
+ __func__, err);
+ }
+}
+
+int qemu_semihosting_console_out(CPUArchState *env, target_ulong addr, int len)
+{
+ GString *s = copy_user_string(env, addr, len);
+ int out = s->len;
+
+ if (use_gdb_syscalls()) {
+ gdb_do_syscall(semihosting_cb, "write,2,%x,%x", addr, s->len);
+ } else {
+ out = qemu_semihosting_log_out(s->str, s->len);
+ }
+
+ g_string_free(s, true);
+ return out;
+}
{
DeviceState *vdev = data;
- object_initialize(vdev, vdev_size, vdev_name);
- object_property_add_child(proxy_obj, "virtio-backend", OBJECT(vdev), NULL);
- object_unref(OBJECT(vdev));
+ object_initialize_child(proxy_obj, "virtio-backend", vdev, vdev_size,
+ vdev_name, &error_abort, NULL);
qdev_alias_all_properties(vdev, proxy_obj);
}
#include "qemu-common.h"
#include "hw/sysbus.h"
+#include "hw/char/pl011.h"
#include "hw/char/bcm2835_aux.h"
#include "hw/display/bcm2835_fb.h"
#include "hw/dma/bcm2835_dma.h"
MemoryRegion ram_alias[4];
qemu_irq irq, fiq;
- SysBusDevice *uart0;
+ PL011State uart0;
BCM2835AuxState aux;
BCM2835FBState fb;
BCM2835DMAState dma;
#ifndef HW_SIFIVE_E_H
#define HW_SIFIVE_E_H
+#include "hw/riscv/sifive_gpio.h"
+
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
#define RISCV_E_SOC(obj) \
OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC)
/*< public >*/
RISCVHartArrayState cpus;
DeviceState *plic;
+ SIFIVEGPIOState gpio;
} SiFiveESoCState;
typedef struct SiFiveEState {
};
enum {
- SIFIVE_E_UART0_IRQ = 3,
- SIFIVE_E_UART1_IRQ = 4
+ SIFIVE_E_UART0_IRQ = 3,
+ SIFIVE_E_UART1_IRQ = 4,
+ SIFIVE_E_GPIO0_IRQ0 = 8
};
#define SIFIVE_E_PLIC_HART_CONFIG "M"
--- /dev/null
+/*
+ * sifive System-on-Chip general purpose input/output register definition
+ *
+ * Copyright 2019 AdaCore
+ *
+ * Base on nrf51_gpio.c:
+ *
+ * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+#ifndef SIFIVE_GPIO_H
+#define SIFIVE_GPIO_H
+
+#include "hw/sysbus.h"
+#define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
+#define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
+
+#define SIFIVE_GPIO_PINS 32
+
+#define SIFIVE_GPIO_SIZE 0x100
+
+#define SIFIVE_GPIO_REG_VALUE 0x000
+#define SIFIVE_GPIO_REG_INPUT_EN 0x004
+#define SIFIVE_GPIO_REG_OUTPUT_EN 0x008
+#define SIFIVE_GPIO_REG_PORT 0x00C
+#define SIFIVE_GPIO_REG_PUE 0x010
+#define SIFIVE_GPIO_REG_DS 0x014
+#define SIFIVE_GPIO_REG_RISE_IE 0x018
+#define SIFIVE_GPIO_REG_RISE_IP 0x01C
+#define SIFIVE_GPIO_REG_FALL_IE 0x020
+#define SIFIVE_GPIO_REG_FALL_IP 0x024
+#define SIFIVE_GPIO_REG_HIGH_IE 0x028
+#define SIFIVE_GPIO_REG_HIGH_IP 0x02C
+#define SIFIVE_GPIO_REG_LOW_IE 0x030
+#define SIFIVE_GPIO_REG_LOW_IP 0x034
+#define SIFIVE_GPIO_REG_IOF_EN 0x038
+#define SIFIVE_GPIO_REG_IOF_SEL 0x03C
+#define SIFIVE_GPIO_REG_OUT_XOR 0x040
+
+typedef struct SIFIVEGPIOState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+
+ qemu_irq irq[SIFIVE_GPIO_PINS];
+ qemu_irq output[SIFIVE_GPIO_PINS];
+
+ uint32_t value; /* Actual value of the pin */
+ uint32_t input_en;
+ uint32_t output_en;
+ uint32_t port; /* Pin value requested by the user */
+ uint32_t pue;
+ uint32_t ds;
+ uint32_t rise_ie;
+ uint32_t rise_ip;
+ uint32_t fall_ie;
+ uint32_t fall_ip;
+ uint32_t high_ie;
+ uint32_t high_ip;
+ uint32_t low_ie;
+ uint32_t low_ip;
+ uint32_t iof_en;
+ uint32_t iof_sel;
+ uint32_t out_xor;
+ uint32_t in;
+ uint32_t in_mask;
+
+} SIFIVEGPIOState;
+
+#endif
FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
#if defined(TARGET_RISCV32)
-#define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
+#define VIRT_CPU TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
-#define VIRT_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
+#define VIRT_CPU TYPE_RISCV_CPU_BASE64
#endif
#endif
--- /dev/null
+/*
+ * Semihosting Console
+ *
+ * Copyright (c) 2019 Linaro Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef _SEMIHOST_CONSOLE_H_
+#define _SEMIHOST_CONSOLE_H_
+
+/**
+ * qemu_semihosting_console_out:
+ * @env: CPUArchState
+ * @s: host address of guest string
+ * @len: length of string or 0 (string is null terminated)
+ *
+ * Send a guest string to the debug console. This may be the remote
+ * gdb session if a softmmu guest is currently being debugged.
+ *
+ * Returns: number of bytes written.
+ */
+int qemu_semihosting_console_out(CPUArchState *env, target_ulong s, int len);
+
+/**
+ * qemu_semihosting_log_out:
+ * @s: pointer to string
+ * @len: length of string
+ *
+ * Send a string to the debug output. Unlike console_out these strings
+ * can't be sent to a remote gdb instance as they don't exist in guest
+ * memory.
+ *
+ * Returns: number of bytes written
+ */
+int qemu_semihosting_log_out(const char *s, int len);
+
+#endif /* _SEMIHOST_CONSOLE_H_ */
{
return NULL;
}
-#else
+
+static inline Chardev *semihosting_get_chardev(void)
+{
+ return NULL;
+}
+#else /* !CONFIG_USER_ONLY */
bool semihosting_enabled(void);
SemihostingTarget semihosting_get_target(void);
const char *semihosting_get_arg(int i);
int semihosting_get_argc(void);
const char *semihosting_get_cmdline(void);
-#endif
+void semihosting_arg_fallback(const char *file, const char *cmd);
+Chardev *semihosting_get_chardev(void);
+/* for vl.c hooks */
+void qemu_semihosting_enable(void);
+int qemu_semihosting_config_options(const char *opt);
+void qemu_semihosting_connect_chardevs(void);
+#endif /* CONFIG_USER_ONLY */
-#endif
+#endif /* SEMIHOST_H */
extern QemuOptsList qemu_net_opts;
extern QemuOptsList qemu_global_opts;
extern QemuOptsList qemu_mon_opts;
+extern QemuOptsList qemu_semihosting_config_opts;
#endif
obj-$(TARGET_HAS_BFLT) += flatload.o
obj-$(TARGET_I386) += vm86.o
obj-$(TARGET_ARM) += arm/nwfpe/
+obj-$(TARGET_ARM) += arm/semihost.o
+obj-$(TARGET_AARCH64) += arm/semihost.o
obj-$(TARGET_M68K) += m68k-sim.o
--- /dev/null
+/*
+ * ARM Semihosting Console Support
+ *
+ * Copyright (c) 2019 Linaro Ltd
+ *
+ * Currently ARM is unique in having support for semihosting support
+ * in linux-user. So for now we implement the common console API but
+ * just for arm linux-user.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "hw/semihosting/console.h"
+#include "qemu.h"
+
+int qemu_semihosting_console_out(CPUArchState *env, target_ulong addr, int len)
+{
+ void *s = lock_user_string(addr);
+ len = write(STDERR_FILENO, s, len ? len : strlen(s));
+ unlock_user(s, addr, 0);
+ return len;
+}
#define RISCV_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
+ /* TYPE_RISCV_CPU_ANY */
return "any";
}
#endif
safe_syscall4(int, clock_nanosleep, const clockid_t, clock, int, flags,
const struct timespec *, req, struct timespec *, rem)
#endif
-#ifdef __NR_msgsnd
-safe_syscall4(int, msgsnd, int, msgid, const void *, msgp, size_t, sz,
- int, flags)
-safe_syscall5(int, msgrcv, int, msgid, void *, msgp, size_t, sz,
- long, msgtype, int, flags)
-safe_syscall4(int, semtimedop, int, semid, struct sembuf *, tsops,
- unsigned, nsops, const struct timespec *, timeout)
-#else
+#if !defined(__NR_msgsnd) || !defined(__NR_msgrcv) || !defined(__NR_semtimedop)
/* This host kernel architecture uses a single ipc syscall; fake up
* wrappers for the sub-operations to hide this implementation detail.
* Annoyingly we can't include linux/ipc.h to get the constant definitions
safe_syscall6(int, ipc, int, call, long, first, long, second, long, third,
void *, ptr, long, fifth)
+#endif
+#ifdef __NR_msgsnd
+safe_syscall4(int, msgsnd, int, msgid, const void *, msgp, size_t, sz,
+ int, flags)
+#else
static int safe_msgsnd(int msgid, const void *msgp, size_t sz, int flags)
{
return safe_ipc(Q_IPCCALL(0, Q_MSGSND), msgid, sz, flags, (void *)msgp, 0);
}
+#endif
+#ifdef __NR_msgrcv
+safe_syscall5(int, msgrcv, int, msgid, void *, msgp, size_t, sz,
+ long, msgtype, int, flags)
+#else
static int safe_msgrcv(int msgid, void *msgp, size_t sz, long type, int flags)
{
return safe_ipc(Q_IPCCALL(1, Q_MSGRCV), msgid, sz, flags, msgp, type);
}
+#endif
+#ifdef __NR_semtimedop
+safe_syscall4(int, semtimedop, int, semid, struct sembuf *, tsops,
+ unsigned, nsops, const struct timespec *, timeout)
+#else
static int safe_semtimedop(int semid, struct sembuf *tsops, unsigned nsops,
const struct timespec *timeout)
{
BlockDriverState *bs;
BdrvDirtyBitmap *bitmap;
DirtyBitmapMigBitmapState *dbms;
- BdrvNextIterator it;
Error *local_err = NULL;
dirty_bitmap_mig_state.bulk_completed = false;
dirty_bitmap_mig_state.prev_bitmap = NULL;
dirty_bitmap_mig_state.no_bitmaps = false;
- for (bs = bdrv_first(&it); bs; bs = bdrv_next(&it)) {
- const char *drive_name = bdrv_get_device_or_node_name(bs);
-
- /* skip automatically inserted nodes */
- while (bs && bs->drv && bs->implicit) {
- bs = backing_bs(bs);
- }
+ for (bs = bdrv_next_all_states(NULL); bs; bs = bdrv_next_all_states(bs)) {
+ const char *name = bdrv_get_device_or_node_name(bs);
for (bitmap = bdrv_dirty_bitmap_next(bs, NULL); bitmap;
bitmap = bdrv_dirty_bitmap_next(bs, bitmap))
continue;
}
- if (drive_name == NULL) {
+ if (!name || strcmp(name, "") == 0) {
error_report("Found bitmap '%s' in unnamed node %p. It can't "
"be migrated", bdrv_dirty_bitmap_name(bitmap), bs);
goto fail;
dbms = g_new0(DirtyBitmapMigBitmapState, 1);
dbms->bs = bs;
- dbms->node_name = drive_name;
+ dbms->node_name = name;
dbms->bitmap = bitmap;
dbms->total_sectors = bdrv_nb_sectors(bs);
dbms->sectors_per_chunk = CHUNK_SIZE * 8 *
'data': { 'node': 'str', 'name': 'str', '*granularity': 'uint32',
'*persistent': 'bool', '*autoload': 'bool', '*disabled': 'bool' } }
+##
+# @BlockDirtyBitmapMergeSource:
+#
+# @local: name of the bitmap, attached to the same node as target bitmap.
+#
+# @external: bitmap with specified node
+#
+# Since: 4.1
+##
+{ 'alternate': 'BlockDirtyBitmapMergeSource',
+ 'data': { 'local': 'str',
+ 'external': 'BlockDirtyBitmap' } }
+
##
# @BlockDirtyBitmapMerge:
#
-# @node: name of device/node which the bitmap is tracking
+# @node: name of device/node which the @target bitmap is tracking
#
# @target: name of the destination dirty bitmap
#
-# @bitmaps: name(s) of the source dirty bitmap(s)
+# @bitmaps: name(s) of the source dirty bitmap(s) at @node and/or fully
+# specifed BlockDirtyBitmap elements. The latter are supported
+# since 4.1.
#
# Since: 4.0
##
{ 'struct': 'BlockDirtyBitmapMerge',
- 'data': { 'node': 'str', 'target': 'str', 'bitmaps': ['str'] } }
+ 'data': { 'node': 'str', 'target': 'str',
+ 'bitmaps': ['BlockDirtyBitmapMergeSource'] } }
##
# @block-dirty-bitmap-add:
#
# @cor_write: a write due to copy-on-read (since 2.11)
#
+# @cluster_alloc_space: an allocation of file space for a cluster (since 4.1)
+#
# Since: 2.9
##
{ 'enum': 'BlkdebugEvent', 'prefix': 'BLKDBG',
'pwritev_rmw_tail', 'pwritev_rmw_after_tail', 'pwritev',
'pwritev_zero', 'pwritev_done', 'empty_image_prepare',
'l1_shrink_write_table', 'l1_shrink_free_l2_clusters',
- 'cor_write'] }
+ 'cor_write', 'cluster_alloc_space'] }
##
# @BlkdebugInjectErrorOptions:
``acl_remove'' commands are deprecated with no replacement. Authorization
for VNC should be performed using the pluggable QAuthZ objects.
+@section System emulator CPUS
+
+@subsection RISC-V ISA CPUs (since 4.1)
+
+The RISC-V cpus with the ISA version in the CPU name have been depcreated. The
+four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
+``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
+option when using the ``rv32`` or ``rv64`` CPUs.
+
+@subsection RISC-V ISA CPUs (since 4.1)
+
+The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nommu`` and
+``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be specified
+via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
+
@section System emulator devices
@subsection bluetooth (since 3.1)
and unable to start post-2004 operating systems. 40p machine type should be
used instead.
+@subsection spike_v1.9.1 and spike_v1.10 (since 4.1)
+
+The version specific Spike machines have been deprecated in favour of the
+generic ``spike`` machine. If you need to specify an older version of the RISC-V
+spec you can use the ``-cpu rv64gcsu,priv_spec=v1.9.1`` command line argument.
+
@section Device options
@subsection Block device options
BlockBackend *blk = NULL, *blk_old_backing = NULL, *blk_new_backing = NULL;
uint8_t *buf_old = NULL;
uint8_t *buf_new = NULL;
- BlockDriverState *bs = NULL;
+ BlockDriverState *bs = NULL, *prefix_chain_bs = NULL;
char *filename;
const char *fmt, *cache, *src_cache, *out_basefmt, *out_baseimg;
int c, flags, src_flags, ret;
/* For safe rebasing we need to compare old and new backing file */
if (!unsafe) {
- char backing_name[PATH_MAX];
QDict *options = NULL;
+ BlockDriverState *base_bs = backing_bs(bs);
- if (bs->backing) {
- if (bs->backing_format[0] != '\0') {
- options = qdict_new();
- qdict_put_str(options, "driver", bs->backing_format);
- }
-
- if (force_share) {
- if (!options) {
- options = qdict_new();
- }
- qdict_put_bool(options, BDRV_OPT_FORCE_SHARE, true);
- }
- bdrv_get_backing_filename(bs, backing_name, sizeof(backing_name));
- blk_old_backing = blk_new_open(backing_name, NULL,
- options, src_flags, &local_err);
- if (!blk_old_backing) {
+ if (base_bs) {
+ blk_old_backing = blk_new(BLK_PERM_CONSISTENT_READ,
+ BLK_PERM_ALL);
+ ret = blk_insert_bs(blk_old_backing, base_bs,
+ &local_err);
+ if (ret < 0) {
error_reportf_err(local_err,
- "Could not open old backing file '%s': ",
- backing_name);
- ret = -1;
+ "Could not reuse old backing file '%s': ",
+ base_bs->filename);
goto out;
}
} else {
goto out;
}
- blk_new_backing = blk_new_open(out_real_path, NULL,
- options, src_flags, &local_err);
- g_free(out_real_path);
- if (!blk_new_backing) {
- error_reportf_err(local_err,
- "Could not open new backing file '%s': ",
- out_baseimg);
- ret = -1;
- goto out;
+ /*
+ * Find out whether we rebase an image on top of a previous image
+ * in its chain.
+ */
+ prefix_chain_bs = bdrv_find_backing_image(bs, out_real_path);
+ if (prefix_chain_bs) {
+ g_free(out_real_path);
+ blk_new_backing = blk_new(BLK_PERM_CONSISTENT_READ,
+ BLK_PERM_ALL);
+ ret = blk_insert_bs(blk_new_backing, prefix_chain_bs,
+ &local_err);
+ if (ret < 0) {
+ error_reportf_err(local_err,
+ "Could not reuse backing file '%s': ",
+ out_baseimg);
+ goto out;
+ }
+ } else {
+ blk_new_backing = blk_new_open(out_real_path, NULL,
+ options, src_flags, &local_err);
+ g_free(out_real_path);
+ if (!blk_new_backing) {
+ error_reportf_err(local_err,
+ "Could not open new backing file '%s': ",
+ out_baseimg);
+ ret = -1;
+ goto out;
+ }
}
}
}
continue;
}
+ if (prefix_chain_bs) {
+ /*
+ * If cluster wasn't changed since prefix_chain, we don't need
+ * to take action
+ */
+ ret = bdrv_is_allocated_above(backing_bs(bs), prefix_chain_bs,
+ offset, n, &n);
+ if (ret < 0) {
+ error_report("error while reading image metadata: %s",
+ strerror(-ret));
+ goto out;
+ }
+ if (!ret) {
+ continue;
+ }
+ }
+
/*
* Read old and new backing file and take into consideration that
* backing files may be smaller than the COW image.
Enable semihosting mode (ARM, M68K, Xtensa, MIPS, Nios II only).
ETEXI
DEF("semihosting-config", HAS_ARG, QEMU_OPTION_semihosting_config,
- "-semihosting-config [enable=on|off][,target=native|gdb|auto][,arg=str[,...]]\n" \
+ "-semihosting-config [enable=on|off][,target=native|gdb|auto][,chardev=id][,arg=str[,...]]\n" \
" semihosting configuration\n",
QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32 |
QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2)
STEXI
-@item -semihosting-config [enable=on|off][,target=native|gdb|auto][,arg=str[,...]]
+@item -semihosting-config [enable=on|off][,target=native|gdb|auto][,chardev=id][,arg=str[,...]]
@findex -semihosting-config
Enable and configure semihosting (ARM, M68K, Xtensa, MIPS, Nios II only).
@table @option
Defines where the semihosting calls will be addressed, to QEMU (@code{native})
or to GDB (@code{gdb}). The default is @code{auto}, which means @code{gdb}
during debug sessions and @code{native} otherwise.
+@item chardev=@var{str1}
+Send the output to a chardev backend output for native or auto output when not in gdb
@item arg=@var{str1},arg=@var{str2},...
Allows the user to pass input arguments, and can be used multiple times to build
up a list. The old-style @code{-kernel}/@code{-append} method of passing a
#include "qapi/qmp/qbool.h"
#include "qapi/qmp/qnum.h"
#include "qapi/qmp/qstring.h"
+#include "qemu/error-report.h"
#define MAX_INTERFACES 32
{
Object *obj = data;
- g_assert(type != NULL);
type_initialize(type);
g_assert(type->instance_size >= sizeof(Object));
{
TypeImpl *type = type_get_by_name(typename);
+ if (!type) {
+ error_report("missing object type '%s'", typename);
+ abort();
+ }
+
object_initialize_with_type(data, size, type);
}
stub-obj-y += ram-block.o
stub-obj-y += ramfb.o
stub-obj-y += fw_cfg.o
+stub-obj-$(CONFIG_SOFTMMU) += semihost.o
--- /dev/null
+/*
+ * Semihosting Stubs for SoftMMU
+ *
+ * Copyright (c) 2019 Linaro Ltd
+ *
+ * Stubs for SoftMMU targets that don't actually do semihosting.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/option.h"
+#include "qemu/error-report.h"
+#include "hw/semihosting/semihost.h"
+
+/* Empty config */
+QemuOptsList qemu_semihosting_config_opts = {
+ .name = "",
+ .head = QTAILQ_HEAD_INITIALIZER(qemu_semihosting_config_opts.head),
+ .desc = {
+ { /* end of list */ }
+ },
+};
+
+/* Queries to config status default to off */
+bool semihosting_enabled(void)
+{
+ return false;
+}
+
+SemihostingTarget semihosting_get_target(void)
+{
+ return SEMIHOSTING_TARGET_AUTO;
+}
+
+/*
+ * All the rest are empty subs. We could g_assert_not_reached() but
+ * that adds extra weight to the final binary. Waste not want not.
+ */
+void qemu_semihosting_enable(void)
+{
+}
+
+int qemu_semihosting_config_options(const char *optarg)
+{
+ return 1;
+}
+
+const char *semihosting_get_arg(int i)
+{
+ return NULL;
+}
+
+int semihosting_get_argc(void)
+{
+ return 0;
+}
+
+const char *semihosting_get_cmdline(void)
+{
+ return NULL;
+}
+
+void semihosting_arg_fallback(const char *file, const char *cmd)
+{
+}
+
+void qemu_semihosting_connect_chardevs(void)
+{
+}
* Arm "Angel" semihosting syscalls
*
* Copyright (c) 2005, 2007 CodeSourcery.
+ * Copyright (c) 2019 Linaro
* Written by Paul Brook.
*
* This program is free software; you can redistribute it and/or modify
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * ARM Semihosting is documented in:
+ * Semihosting for AArch32 and AArch64 Release 2.0
+ * https://static.docs.arm.com/100863/0200/semihosting.pdf
*/
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
+#include "hw/semihosting/console.h"
+#include "qemu/log.h"
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
put_user_u64(val, args + (n) * 8) : \
put_user_u32(val, args + (n) * 4))
+/*
+ * Do a semihosting call.
+ *
+ * The specification always says that the "return register" either
+ * returns a specific value or is corrupted, so we don't need to
+ * report to our caller whether we are returning a value or trying to
+ * leave the register unchanged. We use 0xdeadbeef as the return value
+ * when there isn't a defined return value for the call.
+ */
target_ulong do_arm_semihosting(CPUARMState *env)
{
ARMCPU *cpu = arm_env_get_cpu(env);
return set_swi_errno(ts, close(arg0));
}
case TARGET_SYS_WRITEC:
- {
- char c;
-
- if (get_user_u8(c, args))
- /* FIXME - should this error code be -TARGET_EFAULT ? */
- return (uint32_t)-1;
- /* Write to debug console. stderr is near enough. */
- if (use_gdb_syscalls()) {
- return arm_gdb_syscall(cpu, arm_semi_cb, "write,2,%x,1", args);
- } else {
- return write(STDERR_FILENO, &c, 1);
- }
- }
+ qemu_semihosting_console_out(env, args, 1);
+ return 0xdeadbeef;
case TARGET_SYS_WRITE0:
- if (!(s = lock_user_string(args)))
- /* FIXME - should this error code be -TARGET_EFAULT ? */
- return (uint32_t)-1;
- len = strlen(s);
- if (use_gdb_syscalls()) {
- return arm_gdb_syscall(cpu, arm_semi_cb, "write,2,%x,%x",
- args, len);
- } else {
- ret = write(STDERR_FILENO, s, len);
- }
- unlock_user(s, args, 0);
- return ret;
+ return qemu_semihosting_console_out(env, args, 0);
case TARGET_SYS_WRITE:
GET_ARG(0);
GET_ARG(1);
} else {
s = lock_user(VERIFY_READ, arg1, len, 1);
if (!s) {
- /* FIXME - should this error code be -TARGET_EFAULT ? */
- return (uint32_t)-1;
+ /* Return bytes not written on error */
+ return len;
}
ret = set_swi_errno(ts, write(arg0, s, len));
unlock_user(s, arg1, 0);
- if (ret == (uint32_t)-1)
- return -1;
+ if (ret == (uint32_t)-1) {
+ ret = 0;
+ }
+ /* Return bytes not written */
return len - ret;
}
case TARGET_SYS_READ:
} else {
s = lock_user(VERIFY_WRITE, arg1, len, 0);
if (!s) {
- /* FIXME - should this error code be -TARGET_EFAULT ? */
- return (uint32_t)-1;
+ /* return bytes not read */
+ return len;
}
do {
ret = set_swi_errno(ts, read(arg0, s, len));
} while (ret == -1 && errno == EINTR);
unlock_user(s, arg1, len);
- if (ret == (uint32_t)-1)
- return -1;
+ if (ret == (uint32_t)-1) {
+ ret = 0;
+ }
+ /* Return bytes not read */
return len - ret;
}
case TARGET_SYS_READC:
- /* XXX: Read from debug console. Not implemented. */
+ qemu_log_mask(LOG_UNIMP, "%s: SYS_READC not implemented", __func__);
return 0;
case TARGET_SYS_ISTTY:
GET_ARG(0);
return buf.st_size;
}
case TARGET_SYS_TMPNAM:
- /* XXX: Not implemented. */
+ qemu_log_mask(LOG_UNIMP, "%s: SYS_TMPNAM not implemented", __func__);
return -1;
case TARGET_SYS_REMOVE:
GET_ARG(0);
output_size = ts->info->arg_end - ts->info->arg_start;
if (!output_size) {
- /* We special-case the "empty command line" case (argc==0).
- Just provide the terminating 0. */
+ /*
+ * We special-case the "empty command line" case (argc==0).
+ * Just provide the terminating 0.
+ */
output_size = 1;
}
#endif
if (output_size > input_size) {
- /* Not enough space to store command-line arguments. */
+ /* Not enough space to store command-line arguments. */
return -1;
}
GET_ARG(0);
#ifdef CONFIG_USER_ONLY
- /* Some C libraries assume the heap immediately follows .bss, so
- allocate it using sbrk. */
+ /*
+ * Some C libraries assume the heap immediately follows .bss, so
+ * allocate it using sbrk.
+ */
if (!ts->heap_limit) {
abi_ulong ret;
}
case TARGET_SYS_EXIT:
if (is_a64(env)) {
- /* The A64 version of this call takes a parameter block,
+ /*
+ * The A64 version of this call takes a parameter block,
* so the application-exit type can return a subcode which
* is the exit status code from the application.
*/
ret = 1;
}
} else {
- /* ARM specifies only Stopped_ApplicationExit as normal
- * exit, everything else is considered an error */
+ /*
+ * ARM specifies only Stopped_ApplicationExit as normal
+ * exit, everything else is considered an error
+ */
ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1;
}
gdb_exit(env, ret);
exit(ret);
case TARGET_SYS_SYNCCACHE:
- /* Clean the D-cache and invalidate the I-cache for the specified
+ /*
+ * Clean the D-cache and invalidate the I-cache for the specified
* virtual address range. This is a nop for us since we don't
* implement caches. This is only present on A64.
*/
#include "exec/cpu_ldst.h"
#include "arm_ldst.h"
#include <zlib.h> /* For crc32 */
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "sysemu/cpus.h"
#include "sysemu/kvm.h"
#include "fpu/softfloat.h"
#include "qemu/host-utils.h"
#include "qemu/qemu-print.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "exec/gen-icount.h"
#include "exec/helper-proto.h"
#include "qemu/bitops.h"
#include "qemu/qemu-print.h"
#include "arm_ldst.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "exec/exec-all.h"
#include "qemu/host-utils.h"
#include "sysemu/sysemu.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "exec/log.h"
bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#if defined(CONFIG_USER_ONLY)
obj-y += translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o
-obj-y += gdbstub.o msa_helper.o mips-semi.o
+obj-y += gdbstub.o msa_helper.o
+obj-$(CONFIG_SOFTMMU) += mips-semi.o
obj-$(CONFIG_SOFTMMU) += machine.o cp0_timer.o
obj-$(CONFIG_KVM) += kvm.o
typedef union wr_t wr_t;
union wr_t {
- int8_t b[MSA_WRLEN/8];
- int16_t h[MSA_WRLEN/16];
- int32_t w[MSA_WRLEN/32];
- int64_t d[MSA_WRLEN/64];
+ int8_t b[MSA_WRLEN / 8];
+ int16_t h[MSA_WRLEN / 16];
+ int32_t w[MSA_WRLEN / 32];
+ int64_t d[MSA_WRLEN / 64];
};
typedef union fpr_t fpr_t;
/* FPU/MSA register mapping is not tested on big-endian hosts. */
wr_t wr; /* vector data */
};
-/* define FP_ENDIAN_IDX to access the same location
+/*
+ *define FP_ENDIAN_IDX to access the same location
* in the fpr_t union regardless of the host endianness
*/
#if defined(HOST_WORDS_BIGENDIAN)
#define FCR31_FS 24
#define FCR31_ABS2008 19
#define FCR31_NAN2008 18
-#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
-#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
-#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
+#define SET_FP_COND(num, env) do { ((env).fcr31) |= \
+ ((num) ? (1 << ((num) + 24)) : \
+ (1 << 23)); \
+ } while (0)
+#define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \
+ ~((num) ? (1 << ((num) + 24)) : \
+ (1 << 23)); \
+ } while (0)
+#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \
+ (((env).fcr31 >> 23) & 0x1))
#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
-#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
-#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
-#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
-#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
+#define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \
+ ((v & 0x3f) << 12); \
+ } while (0)
+#define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \
+ ((v & 0x1f) << 7); \
+ } while (0)
+#define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \
+ ((v & 0x1f) << 2); \
+ } while (0)
+#define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0)
#define FP_INEXACT 1
#define FP_UNDERFLOW 2
#define FP_OVERFLOW 4
typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
struct CPUMIPSMVPContext {
int32_t CP0_MVPControl;
-#define CP0MVPCo_CPA 3
-#define CP0MVPCo_STLB 2
-#define CP0MVPCo_VPC 1
-#define CP0MVPCo_EVP 0
+#define CP0MVPCo_CPA 3
+#define CP0MVPCo_STLB 2
+#define CP0MVPCo_VPC 1
+#define CP0MVPCo_EVP 0
int32_t CP0_MVPConf0;
-#define CP0MVPC0_M 31
-#define CP0MVPC0_TLBS 29
-#define CP0MVPC0_GS 28
-#define CP0MVPC0_PCP 27
-#define CP0MVPC0_PTLBE 16
-#define CP0MVPC0_TCA 15
-#define CP0MVPC0_PVPE 10
-#define CP0MVPC0_PTC 0
+#define CP0MVPC0_M 31
+#define CP0MVPC0_TLBS 29
+#define CP0MVPC0_GS 28
+#define CP0MVPC0_PCP 27
+#define CP0MVPC0_PTLBE 16
+#define CP0MVPC0_TCA 15
+#define CP0MVPC0_PVPE 10
+#define CP0MVPC0_PTC 0
int32_t CP0_MVPConf1;
-#define CP0MVPC1_CIM 31
-#define CP0MVPC1_CIF 30
-#define CP0MVPC1_PCX 20
-#define CP0MVPC1_PCP2 10
-#define CP0MVPC1_PCP1 0
+#define CP0MVPC1_CIM 31
+#define CP0MVPC1_CIF 30
+#define CP0MVPC1_PCX 20
+#define CP0MVPC1_PCP2 10
+#define CP0MVPC1_PCP1 0
};
typedef struct mips_def_t mips_def_t;
*/
int32_t CP0_Random;
int32_t CP0_VPEControl;
-#define CP0VPECo_YSI 21
-#define CP0VPECo_GSI 20
-#define CP0VPECo_EXCPT 16
-#define CP0VPECo_TE 15
-#define CP0VPECo_TargTC 0
+#define CP0VPECo_YSI 21
+#define CP0VPECo_GSI 20
+#define CP0VPECo_EXCPT 16
+#define CP0VPECo_TE 15
+#define CP0VPECo_TargTC 0
int32_t CP0_VPEConf0;
-#define CP0VPEC0_M 31
-#define CP0VPEC0_XTC 21
-#define CP0VPEC0_TCS 19
-#define CP0VPEC0_SCS 18
-#define CP0VPEC0_DSC 17
-#define CP0VPEC0_ICS 16
-#define CP0VPEC0_MVP 1
-#define CP0VPEC0_VPA 0
+#define CP0VPEC0_M 31
+#define CP0VPEC0_XTC 21
+#define CP0VPEC0_TCS 19
+#define CP0VPEC0_SCS 18
+#define CP0VPEC0_DSC 17
+#define CP0VPEC0_ICS 16
+#define CP0VPEC0_MVP 1
+#define CP0VPEC0_VPA 0
int32_t CP0_VPEConf1;
-#define CP0VPEC1_NCX 20
-#define CP0VPEC1_NCP2 10
-#define CP0VPEC1_NCP1 0
+#define CP0VPEC1_NCX 20
+#define CP0VPEC1_NCP2 10
+#define CP0VPEC1_NCP1 0
target_ulong CP0_YQMask;
target_ulong CP0_VPESchedule;
target_ulong CP0_VPEScheFBack;
int32_t CP0_VPEOpt;
-#define CP0VPEOpt_IWX7 15
-#define CP0VPEOpt_IWX6 14
-#define CP0VPEOpt_IWX5 13
-#define CP0VPEOpt_IWX4 12
-#define CP0VPEOpt_IWX3 11
-#define CP0VPEOpt_IWX2 10
-#define CP0VPEOpt_IWX1 9
-#define CP0VPEOpt_IWX0 8
-#define CP0VPEOpt_DWX7 7
-#define CP0VPEOpt_DWX6 6
-#define CP0VPEOpt_DWX5 5
-#define CP0VPEOpt_DWX4 4
-#define CP0VPEOpt_DWX3 3
-#define CP0VPEOpt_DWX2 2
-#define CP0VPEOpt_DWX1 1
-#define CP0VPEOpt_DWX0 0
+#define CP0VPEOpt_IWX7 15
+#define CP0VPEOpt_IWX6 14
+#define CP0VPEOpt_IWX5 13
+#define CP0VPEOpt_IWX4 12
+#define CP0VPEOpt_IWX3 11
+#define CP0VPEOpt_IWX2 10
+#define CP0VPEOpt_IWX1 9
+#define CP0VPEOpt_IWX0 8
+#define CP0VPEOpt_DWX7 7
+#define CP0VPEOpt_DWX6 6
+#define CP0VPEOpt_DWX5 5
+#define CP0VPEOpt_DWX4 4
+#define CP0VPEOpt_DWX3 3
+#define CP0VPEOpt_DWX2 2
+#define CP0VPEOpt_DWX1 1
+#define CP0VPEOpt_DWX0 0
/*
* CP0 Register 2
*/
#define CP0PC_PSN 0 /* 5..0 */
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
-#define CP0SRSC0_M 31
-#define CP0SRSC0_SRS3 20
-#define CP0SRSC0_SRS2 10
-#define CP0SRSC0_SRS1 0
+#define CP0SRSC0_M 31
+#define CP0SRSC0_SRS3 20
+#define CP0SRSC0_SRS2 10
+#define CP0SRSC0_SRS1 0
int32_t CP0_SRSConf1_rw_bitmask;
int32_t CP0_SRSConf1;
-#define CP0SRSC1_M 31
-#define CP0SRSC1_SRS6 20
-#define CP0SRSC1_SRS5 10
-#define CP0SRSC1_SRS4 0
+#define CP0SRSC1_M 31
+#define CP0SRSC1_SRS6 20
+#define CP0SRSC1_SRS5 10
+#define CP0SRSC1_SRS4 0
int32_t CP0_SRSConf2_rw_bitmask;
int32_t CP0_SRSConf2;
-#define CP0SRSC2_M 31
-#define CP0SRSC2_SRS9 20
-#define CP0SRSC2_SRS8 10
-#define CP0SRSC2_SRS7 0
+#define CP0SRSC2_M 31
+#define CP0SRSC2_SRS9 20
+#define CP0SRSC2_SRS8 10
+#define CP0SRSC2_SRS7 0
int32_t CP0_SRSConf3_rw_bitmask;
int32_t CP0_SRSConf3;
-#define CP0SRSC3_M 31
-#define CP0SRSC3_SRS12 20
-#define CP0SRSC3_SRS11 10
-#define CP0SRSC3_SRS10 0
+#define CP0SRSC3_M 31
+#define CP0SRSC3_SRS12 20
+#define CP0SRSC3_SRS11 10
+#define CP0SRSC3_SRS10 0
int32_t CP0_SRSConf4_rw_bitmask;
int32_t CP0_SRSConf4;
-#define CP0SRSC4_SRS15 20
-#define CP0SRSC4_SRS14 10
-#define CP0SRSC4_SRS13 0
+#define CP0SRSC4_SRS15 20
+#define CP0SRSC4_SRS14 10
+#define CP0SRSC4_SRS13 0
/*
* CP0 Register 7
*/
/* TMASK defines different execution modes */
#define MIPS_HFLAG_TMASK 0x1F5807FF
#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
- /* The KSU flags must be the lowest bits in hflags. The flag order
- must be the same as defined for CP0 Status. This allows to use
- the bits as the value of mmu_idx. */
+ /*
+ * The KSU flags must be the lowest bits in hflags. The flag order
+ * must be the same as defined for CP0 Status. This allows to use
+ * the bits as the value of mmu_idx.
+ */
#define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
#define MIPS_HFLAG_UM 0x00002 /* user mode flag */
#define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
#define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
#define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
#define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
- /* True if the MIPS IV COP1X instructions can be used. This also
- controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
- and RSQRT.D. */
+ /*
+ * True if the MIPS IV COP1X instructions can be used. This also
+ * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
+ * and RSQRT.D.
+ */
#define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
#define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
#define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
#define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
#define MIPS_HFLAG_M16_SHIFT 10
- /* If translation is interrupted between the branch instruction and
+ /*
+ * If translation is interrupted between the branch instruction and
* the delay slot, record what type of branch it is so that we can
* resume translation properly. It might be possible to reduce
- * this from three bits to two. */
+ * this from three bits to two.
+ */
#define MIPS_HFLAG_BMASK_BASE 0x803800
#define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
#define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
-/* MMU modes definitions. We carefully match the indices with our
- hflags layout. */
+/*
+ * MMU modes definitions. We carefully match the indices with our
+ * hflags layout.
+ */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _super
#define MMU_MODE2_SUFFIX _user
}
}
-static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
+static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
{
return hflags_mmu_index(env->hflags);
}
#include "exec/cpu-all.h"
-/* Memory access type :
+/*
+ * Memory access type :
* may be needed for precise access rights control and precise exceptions.
*/
enum {
void itc_reconfigure(struct MIPSITUState *tag);
/* helper.c */
-target_ulong exception_resume_pc (CPUMIPSState *env);
+target_ulong exception_resume_pc(CPUMIPSState *env);
static inline void restore_snan_bit_mode(CPUMIPSState *env)
{
target_ulong address, int rw, int access_type)
{
*physical = address;
- *prot = PAGE_READ | PAGE_WRITE;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
else
*physical = address;
- *prot = PAGE_READ | PAGE_WRITE;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
*prot = PAGE_READ;
if (n ? tlb->D1 : tlb->D0)
*prot |= PAGE_WRITE;
+ if (!(n ? tlb->XI1 : tlb->XI0)) {
+ *prot |= PAGE_EXEC;
+ }
return TLBRET_MATCH;
}
return TLBRET_DIRTY;
} else {
/* The segment is unmapped */
*physical = physical_base | (real_address & segmask);
- *prot = PAGE_READ | PAGE_WRITE;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
}
}
if (ret == TLBRET_MATCH) {
tlb_set_page(cs, address & TARGET_PAGE_MASK,
- physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
+ physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
return true;
}
access_type, mips_access_type, mmu_idx);
if (ret == TLBRET_MATCH) {
tlb_set_page(cs, address & TARGET_PAGE_MASK,
- physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
+ physical & TARGET_PAGE_MASK, prot,
mmu_idx, TARGET_PAGE_SIZE);
return true;
}
DEF_HELPER_2(raise_exception, noreturn, env, i32)
DEF_HELPER_1(raise_exception_debug, noreturn, env)
+#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(do_semihosting, void, env)
+#endif
#ifdef TARGET_MIPS64
DEF_HELPER_4(sdl, void, env, tl, tl, int)
DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_copy_s_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32)
+
DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)
DEF_HELPER_2(msa_cfcmsa, tl, env, i32)
DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_insert_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32)
#include "qemu/log.h"
#include "exec/helper-proto.h"
#include "exec/softmmu-semi.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
+#include "hw/semihosting/console.h"
typedef enum UHIOp {
UHI_exit = 1,
p2 = strstr(p, "%d");
if (p2) {
int char_num = p2 - p;
- char *buf = g_malloc(char_num + 1);
- strncpy(buf, p, char_num);
- buf[char_num] = '\0';
- gpr[2] = printf("%s%d%s", buf, (int)gpr[5], p2 + 2);
- g_free(buf);
+ GString *s = g_string_new_len(p, char_num);
+ g_string_append_printf(s, "%d%s", (int)gpr[5], p2 + 2);
+ gpr[2] = qemu_semihosting_log_out(s->str, s->len);
+ g_string_free(s, true);
} else {
- gpr[2] = printf("%s", p);
+ gpr[2] = qemu_semihosting_log_out(p, strlen(p));
}
FREE_TARGET_STRING(p, gpr[4]);
break;
if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
return DF_MIN_INT(df);
}
- return arg2 ? arg1 / arg2 : 0;
+ return arg2 ? arg1 / arg2
+ : arg1 >= 0 ? -1 : 1;
}
static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
uint64_t u_arg2 = UNSIGNED(arg2, df);
- return u_arg2 ? u_arg1 / u_arg2 : 0;
+ return arg2 ? u_arg1 / u_arg2 : -1;
}
static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
return 0;
}
- return arg2 ? arg1 % arg2 : 0;
+ return arg2 ? arg1 % arg2 : arg1;
}
static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
uint64_t u_arg2 = UNSIGNED(arg2, df);
- return u_arg2 ? u_arg1 % u_arg2 : 0;
+ return u_arg2 ? u_arg1 % u_arg2 : u_arg1;
}
#define SIGNED_EVEN(a, df) \
msa_splat_df(df, pwd, pws, n);
}
-void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
- uint32_t ws, uint32_t n)
+void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
{
- n %= DF_ELEMENTS(df);
+ n %= 16;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 8) {
+ n = 8 - n - 1;
+ } else {
+ n = 24 - n - 1;
+ }
+#endif
+ env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
+}
- switch (df) {
- case DF_BYTE:
- env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
- break;
- case DF_HALF:
- env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
- break;
- case DF_WORD:
- env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
- break;
-#ifdef TARGET_MIPS64
- case DF_DOUBLE:
- env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
- break;
+void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
+{
+ n %= 8;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 4) {
+ n = 4 - n - 1;
+ } else {
+ n = 12 - n - 1;
+ }
#endif
- default:
- assert(0);
+ env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
+}
+
+void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
+{
+ n %= 4;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 2) {
+ n = 2 - n - 1;
+ } else {
+ n = 6 - n - 1;
}
+#endif
+ env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
}
-void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
- uint32_t ws, uint32_t n)
+void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
{
- n %= DF_ELEMENTS(df);
+ n %= 2;
+ env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
+}
- switch (df) {
- case DF_BYTE:
- env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
- break;
- case DF_HALF:
- env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
- break;
- case DF_WORD:
- env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
- break;
-#ifdef TARGET_MIPS64
- case DF_DOUBLE:
- env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
- break;
+void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
+{
+ n %= 16;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 8) {
+ n = 8 - n - 1;
+ } else {
+ n = 24 - n - 1;
+ }
#endif
- default:
- assert(0);
+ env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
+}
+
+void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
+{
+ n %= 8;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 4) {
+ n = 4 - n - 1;
+ } else {
+ n = 12 - n - 1;
+ }
+#endif
+ env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
+}
+
+void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd,
+ uint32_t ws, uint32_t n)
+{
+ n %= 4;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 2) {
+ n = 2 - n - 1;
+ } else {
+ n = 6 - n - 1;
}
+#endif
+ env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
}
-void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
+void helper_msa_insert_b(CPUMIPSState *env, uint32_t wd,
uint32_t rs_num, uint32_t n)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
target_ulong rs = env->active_tc.gpr[rs_num];
+ n %= 16;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 8) {
+ n = 8 - n - 1;
+ } else {
+ n = 24 - n - 1;
+ }
+#endif
+ pwd->b[n] = (int8_t)rs;
+}
- switch (df) {
- case DF_BYTE:
- pwd->b[n] = (int8_t)rs;
- break;
- case DF_HALF:
- pwd->h[n] = (int16_t)rs;
- break;
- case DF_WORD:
- pwd->w[n] = (int32_t)rs;
- break;
- case DF_DOUBLE:
- pwd->d[n] = (int64_t)rs;
- break;
- default:
- assert(0);
+void helper_msa_insert_h(CPUMIPSState *env, uint32_t wd,
+ uint32_t rs_num, uint32_t n)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ target_ulong rs = env->active_tc.gpr[rs_num];
+ n %= 8;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 4) {
+ n = 4 - n - 1;
+ } else {
+ n = 12 - n - 1;
}
+#endif
+ pwd->h[n] = (int16_t)rs;
+}
+
+void helper_msa_insert_w(CPUMIPSState *env, uint32_t wd,
+ uint32_t rs_num, uint32_t n)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ target_ulong rs = env->active_tc.gpr[rs_num];
+ n %= 4;
+#if defined(HOST_WORDS_BIGENDIAN)
+ if (n < 2) {
+ n = 2 - n - 1;
+ } else {
+ n = 6 - n - 1;
+ }
+#endif
+ pwd->w[n] = (int32_t)rs;
+}
+
+void helper_msa_insert_d(CPUMIPSState *env, uint32_t wd,
+ uint32_t rs_num, uint32_t n)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ target_ulong rs = env->active_tc.gpr[rs_num];
+ n %= 2;
+ pwd->d[n] = (int64_t)rs;
}
void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
#define MEMOP_IDX(DF)
#endif
-#define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
-void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
- target_ulong addr) \
-{ \
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
- wr_t wx; \
- int i; \
- MEMOP_IDX(DF) \
- for (i = 0; i < DF_ELEMENTS(DF); i++) { \
- wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
- } \
- memcpy(pwd, &wx, sizeof(wr_t)); \
+void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_BYTE)
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
+ pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
+ pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
+ pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
+ pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
+ pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
+ pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
+ pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
+ pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
+ pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
+ pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
+ pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
+ pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
+ pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
+ pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
+ pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
+#else
+ pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
+ pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
+ pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
+ pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
+ pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
+ pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
+ pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
+ pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
+ pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
+ pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
+ pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
+ pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
+ pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
+ pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
+ pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
+ pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
+ pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
+ pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
+ pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
+ pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
+ pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
+ pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
+ pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
+ pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
+ pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
+ pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
+ pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
+ pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
+ pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
+ pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
+ pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
+#else
+ pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
+ pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
+ pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
+ pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
+ pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
+ pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
+ pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
+ pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
+ pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
+ pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
+ pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
+ pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
+ pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
+ pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
+ pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
+ pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
+#endif
+#endif
+}
+
+void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_HALF)
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
+ pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
+ pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
+ pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
+ pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
+ pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
+ pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
+ pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
+#else
+ pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
+ pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
+ pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
+ pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
+ pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
+ pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
+ pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
+ pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF));
+ pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF));
+ pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF));
+ pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF));
+ pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF));
+ pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF));
+ pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF));
+ pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF));
+#else
+ pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF));
+ pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF));
+ pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF));
+ pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF));
+ pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF));
+ pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF));
+ pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF));
+ pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF));
+#endif
+#endif
}
+void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_WORD)
#if !defined(CONFIG_USER_ONLY)
-MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETPC())
-MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETPC())
-MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETPC())
-MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETPC())
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
+ pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
+ pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
+ pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
#else
-MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
-MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
-MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
-MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
+ pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
+ pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
+ pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
+ pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD));
+ pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD));
+ pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD));
+ pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD));
+#else
+ pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD));
+ pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD));
+ pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD));
+ pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD));
+#endif
+#endif
+}
+
+void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ MEMOP_IDX(DF_DOUBLE)
+#if !defined(CONFIG_USER_ONLY)
+ pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC());
+ pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC());
+#else
+ pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE));
+ pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE));
+#endif
+}
#define MSA_PAGESPAN(x) \
((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
#endif
}
-#define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
-void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
- target_ulong addr) \
-{ \
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
- int mmu_idx = cpu_mmu_index(env, false); \
- int i; \
- MEMOP_IDX(DF) \
- ensure_writable_pages(env, addr, mmu_idx, GETPC()); \
- for (i = 0; i < DF_ELEMENTS(DF); i++) { \
- ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
- } \
+void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_BYTE)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC());
+#else
+ helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC());
+ helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]);
+ cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]);
+ cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]);
+ cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]);
+ cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]);
+ cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]);
+ cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]);
+ cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]);
+ cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]);
+ cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]);
+ cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]);
+ cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]);
+ cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]);
+ cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]);
+ cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]);
+ cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]);
+#else
+ cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]);
+ cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]);
+ cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]);
+ cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]);
+ cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]);
+ cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]);
+ cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]);
+ cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]);
+ cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]);
+ cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]);
+ cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]);
+ cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]);
+ cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]);
+ cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]);
+ cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]);
+ cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]);
+#endif
+#endif
+}
+
+void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_HALF)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC());
+#else
+ helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC());
+ helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC());
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]);
+ cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]);
+ cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]);
+ cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]);
+ cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]);
+ cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]);
+ cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]);
+ cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]);
+#else
+ cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]);
+ cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]);
+ cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]);
+ cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]);
+ cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]);
+ cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]);
+ cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]);
+ cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]);
+#endif
+#endif
}
+void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_WORD)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
#if !defined(CONFIG_USER_ONLY)
-MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETPC())
-MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETPC())
-MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETPC())
-MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETPC())
+#if !defined(HOST_WORDS_BIGENDIAN)
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[0]);
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[1]);
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[2]);
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[3]);
#else
-MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
-MSA_ST_DF(DF_HALF, h, cpu_stw_data)
-MSA_ST_DF(DF_WORD, w, cpu_stl_data)
-MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[0]);
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[1]);
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[2]);
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[3]);
+#endif
+#else
+#if !defined(HOST_WORDS_BIGENDIAN)
+ cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]);
+ cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]);
+ cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]);
+ cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]);
+#else
+ cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]);
+ cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]);
+ cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]);
+ cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]);
+#endif
#endif
+}
+
+void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
+ target_ulong addr)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ int mmu_idx = cpu_mmu_index(env, false);
+
+ MEMOP_IDX(DF_DOUBLE)
+ ensure_writable_pages(env, addr, mmu_idx, GETPC());
+#if !defined(CONFIG_USER_ONLY)
+ helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC());
+ helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC());
+#else
+ cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]);
+ cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
+#endif
+}
void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
{
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "target/mips/trace.h"
#include "trace-tcg.h"
#endif
}
+#ifdef CONFIG_USER_ONLY
+/* The above should dead-code away any calls to this..*/
+static inline void gen_helper_do_semihosting(void *env)
+{
+ g_assert_not_reached();
+}
+#endif
+
static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
{
int rx, ry;
generate_exception_end(ctx, EXCP_RI);
break;
}
+ if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
+ (df == DF_WORD)) {
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
#endif
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
if (likely(wd != 0)) {
- gen_helper_msa_copy_s_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn);
+ break;
+ case DF_WORD:
+ gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_DOUBLE:
+ gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
}
break;
case OPC_COPY_U_df:
if (likely(wd != 0)) {
- gen_helper_msa_copy_u_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_copy_u_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_copy_u_h(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_WORD:
+ gen_helper_msa_copy_u_w(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
}
break;
case OPC_INSERT_df:
- gen_helper_msa_insert_df(cpu_env, tdf, twd, tws, tn);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
+ break;
+ case DF_HALF:
+ gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
+ break;
+ case DF_WORD:
+ gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
+ break;
+#if defined(TARGET_MIPS64)
+ case DF_DOUBLE:
+ gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
+ break;
+#endif
+ default:
+ assert(0);
+ }
break;
}
break;
#include "exec/cpu_ldst.h"
#include "exec/log.h"
#include "exec/helper-proto.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#if defined(CONFIG_USER_ONLY)
decode32-y = $(SRC_PATH)/target/riscv/insn32.decode
decode32-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn32-64.decode
+decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
+decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
+decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
+
target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
$(call quiet-command, \
- $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \
- "GEN", $(TARGET_DIR)$@)
+ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
+ $(decode32-y), "GEN", $(TARGET_DIR)$@)
-target/riscv/decode_insn16.inc.c: \
- $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE)
+target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
$(call quiet-command, \
- $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<, \
- "GEN", $(TARGET_DIR)$@)
+ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
+ --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
target/riscv/decode_insn16.inc.c
#include "cpu.h"
#include "exec/exec-all.h"
#include "qapi/error.h"
+#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
/* RISC-V CPU definitions */
static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
const char * const riscv_int_regnames[] = {
- "zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ",
- "s0 ", "s1 ", "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ",
- "a6 ", "a7 ", "s2 ", "s3 ", "s4 ", "s5 ", "s6 ", "s7 ",
- "s8 ", "s9 ", "s10 ", "s11 ", "t3 ", "t4 ", "t5 ", "t6 "
+ "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
+ "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
+ "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
+ "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
};
const char * const riscv_fpr_regnames[] = {
- "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ", "ft7 ",
- "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ", "fa5 ",
- "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ", "fs7 ",
- "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10", "ft11"
+ "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
+ "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
+ "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
+ "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
};
const char * const riscv_excp_names[] = {
#if defined(TARGET_RISCV32)
+static void riscv_base32_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+}
+
static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
#elif defined(TARGET_RISCV64)
+static void riscv_base64_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+}
+
static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
static void riscv_cpu_realize(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
+ RISCVCPU *cpu = RISCV_CPU(dev);
+ CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
+ int priv_version = PRIV_VERSION_1_10_0;
+ int user_version = USER_VERSION_2_02_0;
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
return;
}
+ if (cpu->cfg.priv_spec) {
+ if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
+ priv_version = PRIV_VERSION_1_10_0;
+ } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
+ priv_version = PRIV_VERSION_1_09_1;
+ } else {
+ error_setg(errp,
+ "Unsupported privilege spec version '%s'",
+ cpu->cfg.priv_spec);
+ return;
+ }
+ }
+
+ if (cpu->cfg.user_spec) {
+ if (!g_strcmp0(cpu->cfg.user_spec, "v2.02.0")) {
+ user_version = USER_VERSION_2_02_0;
+ } else {
+ error_setg(errp,
+ "Unsupported user spec version '%s'",
+ cpu->cfg.user_spec);
+ return;
+ }
+ }
+
+ set_versions(env, user_version, priv_version);
+ set_resetvec(env, DEFAULT_RSTVEC);
+
+ if (cpu->cfg.mmu) {
+ set_feature(env, RISCV_FEATURE_MMU);
+ }
+
+ if (cpu->cfg.pmp) {
+ set_feature(env, RISCV_FEATURE_PMP);
+ }
+
riscv_cpu_register_gdb_regs_for_features(cs);
qemu_init_vcpu(cs);
.unmigratable = 1,
};
+static Property riscv_cpu_properties[] = {
+ DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+ DEFINE_PROP_STRING("user_spec", RISCVCPU, cfg.user_spec),
+ DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+ DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
#endif
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
+ dc->props = riscv_cpu_properties;
}
char *riscv_isa_string(RISCVCPU *cpu)
},
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init)
#elif defined(TARGET_RISCV64)
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
+#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
+#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
CPUState parent_obj;
/*< public >*/
CPURISCVState env;
+
+ /* Configuration Settings */
+ struct {
+ char *priv_spec;
+ char *user_spec;
+ bool mmu;
+ bool pmp;
+ } cfg;
} RISCVCPU;
static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env)
#define CSR_DPC 0x7b1
#define CSR_DSCRATCH 0x7b2
+/* Hpervisor CSRs */
+#define CSR_HSTATUS 0xa00
+#define CSR_HEDELEG 0xa02
+#define CSR_HIDELEG 0xa03
+#define CSR_HGATP 0xa80
+
+#if defined(TARGET_RISCV32)
+#define HGATP_MODE SATP32_MODE
+#define HGATP_ASID SATP32_ASID
+#define HGATP_PPN SATP32_PPN
+#endif
+#if defined(TARGET_RISCV64)
+#define HGATP_MODE SATP64_MODE
+#define HGATP_ASID SATP64_ASID
+#define HGATP_PPN SATP64_PPN
+#endif
+
/* Performance Counters */
#define CSR_MHPMCOUNTER3 0xb03
#define CSR_MHPMCOUNTER4 0xb04
#define CSR_MHPMCOUNTER31H 0xb9f
/* Legacy Hypervisor Trap Setup (priv v1.9.1) */
-#define CSR_HSTATUS 0x200
-#define CSR_HEDELEG 0x202
-#define CSR_HIDELEG 0x203
#define CSR_HIE 0x204
#define CSR_HTVEC 0x205
/* mstatus CSR bits */
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
-#define MSTATUS_HIE 0x00000004
#define MSTATUS_MIE 0x00000008
#define MSTATUS_UPIE 0x00000010
#define MSTATUS_SPIE 0x00000020
-#define MSTATUS_HPIE 0x00000040
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
-#define MSTATUS_HPP 0x00000600
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
#define MSTATUS_XS 0x00018000
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
+#define MSTATUS_MTL 0x4000000000ULL
+#define MSTATUS_MPV 0x8000000000ULL
#define MSTATUS64_UXL 0x0000000300000000ULL
#define MSTATUS64_SXL 0x0000000C00000000ULL
#define SSTATUS_SD SSTATUS64_SD
#endif
+/* hstatus CSR bits */
+#define HSTATUS_SPRV 0x00000001
+#define HSTATUS_STL 0x00000040
+#define HSTATUS_SPV 0x00000080
+#define HSTATUS_SP2P 0x00000100
+#define HSTATUS_SP2V 0x00000200
+#define HSTATUS_VTVM 0x00100000
+#define HSTATUS_VTSR 0x00400000
+
+#define HSTATUS32_WPRI 0xFF8FF87E
+#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
+
+#if defined(TARGET_RISCV32)
+#define HSTATUS_WPRI HSTATUS32_WPRI
+#elif defined(TARGET_RISCV64)
+#define HSTATUS_WPRI HSTATUS64_WPRI
+#endif
+
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
-#define PRV_H 2
+#define PRV_H 2 /* Reserved */
#define PRV_M 3
/* RV32 satp CSR field masks */
}
}
-/* iothread_mutex must be held */
+struct CpuAsyncInfo {
+ uint32_t new_mip;
+};
+
+static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state,
+ run_on_cpu_data data)
+{
+ CPURISCVState *env = &RISCV_CPU(target_cpu_state)->env;
+ RISCVCPU *cpu = riscv_env_get_cpu(env);
+ struct CpuAsyncInfo *info = (struct CpuAsyncInfo *) data.host_ptr;
+
+ if (info->new_mip) {
+ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
+ }
+
+ g_free(info);
+}
+
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
{
CPURISCVState *env = &cpu->env;
+ CPUState *cs = CPU(cpu);
+ struct CpuAsyncInfo *info;
uint32_t old, new, cmp = atomic_read(&env->mip);
do {
cmp = atomic_cmpxchg(&env->mip, old, new);
} while (old != cmp);
- if (new) {
- cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
- } else {
- cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
- }
+ info = g_new(struct CpuAsyncInfo, 1);
+ info->new_mip = new;
+
+ async_run_on_cpu(cs, riscv_cpu_update_mip_irqs_async,
+ RUN_ON_CPU_HOST_PTR(info));
return old;
}
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
- env->scause = cause | ~(((target_ulong)-1) >> async);
+ env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
env->sepc = env->pc;
env->sbadaddr = tval;
env->pc = (env->stvec >> 2 << 2) +
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
#if defined(TARGET_RISCV32)
static const char valid_vm_1_09[16] = {
{
target_ulong mstatus = env->mstatus;
target_ulong mask = 0;
- target_ulong mpp = get_field(val, MSTATUS_MPP);
/* flush tlb on mstatus fields that affect VM */
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
MSTATUS_VM : 0);
}
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
+ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
MSTATUS_MPRV | MSTATUS_SUM)) {
tlb_flush(CPU(riscv_env_get_cpu(env)));
}
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW;
- }
-
- /* silenty discard mstatus.mpp writes for unsupported modes */
- if (mpp == PRV_H ||
- (!riscv_has_ext(env, RVS) && mpp == PRV_S) ||
- (!riscv_has_ext(env, RVU) && mpp == PRV_U)) {
- mask &= ~MSTATUS_MPP;
+#if defined(TARGET_RISCV64)
+ /*
+ * RV32: MPV and MTL are not in mstatus. The current plan is to
+ * add them to mstatush. For now, we just don't support it.
+ */
+ mask |= MSTATUS_MPP | MSTATUS_MPV;
+#endif
}
mstatus = (mstatus & ~mask) | (val & mask);
uint32_t old_mip;
if (mask) {
- qemu_mutex_lock_iothread();
old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
- qemu_mutex_unlock_iothread();
} else {
old_mip = atomic_read(&env->mip);
}
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- return rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
- write_mask & env->mideleg);
+ int ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
+ write_mask & env->mideleg & sip_writable_mask);
+ *ret_value &= env->mideleg;
+ return ret;
}
/* Supervisor Protection and Translation */
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
} else {
- tlb_flush(CPU(riscv_env_get_cpu(env)));
+ if((val ^ env->satp) & SATP_ASID) {
+ tlb_flush(CPU(riscv_env_get_cpu(env)));
+ }
env->satp = val;
}
}
--- /dev/null
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# *** RV32C Standard Extension (Quadrant 0) ***
+flw 011 ... ... .. ... 00 @cl_w
+fsw 111 ... ... .. ... 00 @cs_w
+
+# *** RV32C Standard Extension (Quadrant 1) ***
+jal 001 ........... 01 @cj rd=1 # C.JAL
+
+# *** RV32C Standard Extension (Quadrant 2) ***
+flw 011 . ..... ..... 10 @c_lwsp
+fsw 111 . ..... ..... 10 @c_swsp
--- /dev/null
+#
+# RISC-V translation routines for the RVXI Base Integer Instruction Set.
+#
+# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2 or later, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program. If not, see <http://www.gnu.org/licenses/>.
+
+# *** RV64C Standard Extension (Quadrant 0) ***
+ld 011 ... ... .. ... 00 @cl_d
+sd 111 ... ... .. ... 00 @cs_d
+
+# *** RV64C Standard Extension (Quadrant 1) ***
+{
+ illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
+ addiw 001 . ..... ..... 01 @ci
+}
+subw 100 1 11 ... 00 ... 01 @cs_2
+addw 100 1 11 ... 01 ... 01 @cs_2
+
+# *** RV64C Standard Extension (Quadrant 2) ***
+{
+ illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
+ ld 011 . ..... ..... 10 @c_ldsp
+}
+sd 111 . ..... ..... 10 @c_sdsp
%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
-%nzuimm_6bit 12:1 2:5
+%shimm_6bit 12:1 2:5 !function=ex_rvc_shifti
%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3
%imm_lui 12:s1 2:5 !function=ex_shift_12
+# Argument sets imported from insn32.decode:
+&empty !extern
+&r rd rs1 rs2 !extern
+&i imm rs1 rd !extern
+&s imm rs1 rs2 !extern
+&j imm rd !extern
+&b imm rs2 rs1 !extern
+&u imm rd !extern
+&shift shamt rs1 rd !extern
-# Argument sets:
-&cl rs1 rd
-&cl_dw uimm rs1 rd
-&ci imm rd
-&ciw nzuimm rd
-&cs rs1 rs2
-&cs_dw uimm rs1 rs2
-&cb imm rs1
-&cr rd rs2
-&cj imm
-&c_shift shamt rd
-
-&c_ld uimm rd
-&c_sd uimm rs2
-
-&caddi16sp_lui imm_lui imm_addi16sp rd
-&cflwsp_ldsp uimm_flwsp uimm_ldsp rd
-&cfswsp_sdsp uimm_fswsp uimm_sdsp rs2
# Formats 16:
-@cr .... ..... ..... .. &cr rs2=%rs2_5 %rd
-@ci ... . ..... ..... .. &ci imm=%imm_ci %rd
-@ciw ... ........ ... .. &ciw nzuimm=%nzuimm_ciw rd=%rs2_3
-@cl_d ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
-@cl_w ... ... ... .. ... .. &cl_dw uimm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
-@cl ... ... ... .. ... .. &cl rs1=%rs1_3 rd=%rs2_3
-@cs ... ... ... .. ... .. &cs rs1=%rs1_3 rs2=%rs2_3
-@cs_2 ... ... ... .. ... .. &cr rd=%rs1_3 rs2=%rs2_3
-@cs_d ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
-@cs_w ... ... ... .. ... .. &cs_dw uimm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
-@cb ... ... ... .. ... .. &cb imm=%imm_cb rs1=%rs1_3
-@cj ... ........... .. &cj imm=%imm_cj
-
-@c_ld ... . ..... ..... .. &c_ld uimm=%uimm_6bit_ld %rd
-@c_lw ... . ..... ..... .. &c_ld uimm=%uimm_6bit_lw %rd
-@c_sd ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sd rs2=%rs2_5
-@c_sw ... . ..... ..... .. &c_sd uimm=%uimm_6bit_sw rs2=%rs2_5
-
-@c_addi16sp_lui ... . ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16sp %rd
-@c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=%uimm_6bit_lw \
- uimm_ldsp=%uimm_6bit_ld %rd
-@c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=%uimm_6bit_sw \
- uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5
-
-@c_shift ... . .. ... ..... .. &c_shift rd=%rs1_3 shamt=%nzuimm_6bit
-@c_shift2 ... . .. ... ..... .. &c_shift rd=%rd shamt=%nzuimm_6bit
-
-@c_andi ... . .. ... ..... .. &ci imm=%imm_ci rd=%rs1_3
-
-# *** RV64C Standard Extension (Quadrant 0) ***
-c_addi4spn 000 ........ ... 00 @ciw
-c_fld 001 ... ... .. ... 00 @cl_d
-c_lw 010 ... ... .. ... 00 @cl_w
-c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm manually
-c_fsd 101 ... ... .. ... 00 @cs_d
-c_sw 110 ... ... .. ... 00 @cs_w
-c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm manually
-
-# *** RV64C Standard Extension (Quadrant 1) ***
-c_addi 000 . ..... ..... 01 @ci
-c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm manually
-c_li 010 . ..... ..... 01 @ci
-c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with C.LUI
-c_srli 100 . 00 ... ..... 01 @c_shift
-c_srai 100 . 01 ... ..... 01 @c_shift
-c_andi 100 . 10 ... ..... 01 @c_andi
-c_sub 100 0 11 ... 00 ... 01 @cs_2
-c_xor 100 0 11 ... 01 ... 01 @cs_2
-c_or 100 0 11 ... 10 ... 01 @cs_2
-c_and 100 0 11 ... 11 ... 01 @cs_2
-c_subw 100 1 11 ... 00 ... 01 @cs_2
-c_addw 100 1 11 ... 01 ... 01 @cs_2
-c_j 101 ........... 01 @cj
-c_beqz 110 ... ... ..... 01 @cb
-c_bnez 111 ... ... ..... 01 @cb
-
-# *** RV64C Standard Extension (Quadrant 2) ***
-c_slli 000 . ..... ..... 10 @c_shift2
-c_fldsp 001 . ..... ..... 10 @c_ld
-c_lwsp 010 . ..... ..... 10 @c_lw
-c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWSP:RV32
-c_jr_mv 100 0 ..... ..... 10 @cr
-c_ebreak_jalr_add 100 1 ..... ..... 10 @cr
-c_fsdsp 101 ...... ..... 10 @c_sd
-c_swsp 110 . ..... ..... 10 @c_sw
-c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWSP:RV32
+@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
+@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
+@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
+@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
+@cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3
+@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
+@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
+@cj ... ........... .. &j imm=%imm_cj
+@cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0
+
+@c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd
+@c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
+@c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
+@c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
+@c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd
+@c_lui ... . ..... ..... .. &u imm=%imm_lui %rd
+@c_jalr ... . ..... ..... .. &i imm=0 rs1=%rd
+@c_mv ... . ..... ..... .. &i imm=0 rs1=%rs2_5 %rd
+
+@c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
+@c_addi16sp ... . ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
+
+@c_shift ... . .. ... ..... .. \
+ &shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
+@c_shift2 ... . .. ... ..... .. \
+ &shift rd=%rd rs1=%rd shamt=%shimm_6bit
+
+@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
+
+# *** RV32/64C Standard Extension (Quadrant 0) ***
+{
+ # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
+ illegal 000 000 000 00 --- 00
+ addi 000 ... ... .. ... 00 @c_addi4spn
+}
+fld 001 ... ... .. ... 00 @cl_d
+lw 010 ... ... .. ... 00 @cl_w
+fsd 101 ... ... .. ... 00 @cs_d
+sw 110 ... ... .. ... 00 @cs_w
+
+# *** RV32/64C Standard Extension (Quadrant 1) ***
+addi 000 . ..... ..... 01 @ci
+addi 010 . ..... ..... 01 @c_li
+{
+ illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
+ addi 011 . 00010 ..... 01 @c_addi16sp
+ lui 011 . ..... ..... 01 @c_lui
+}
+srli 100 . 00 ... ..... 01 @c_shift
+srai 100 . 01 ... ..... 01 @c_shift
+andi 100 . 10 ... ..... 01 @c_andi
+sub 100 0 11 ... 00 ... 01 @cs_2
+xor 100 0 11 ... 01 ... 01 @cs_2
+or 100 0 11 ... 10 ... 01 @cs_2
+and 100 0 11 ... 11 ... 01 @cs_2
+jal 101 ........... 01 @cj rd=0 # C.J
+beq 110 ... ... ..... 01 @cb_z
+bne 111 ... ... ..... 01 @cb_z
+
+# *** RV32/64C Standard Extension (Quadrant 2) ***
+slli 000 . ..... ..... 10 @c_shift2
+fld 001 . ..... ..... 10 @c_ldsp
+{
+ illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
+ lw 010 . ..... ..... 10 @c_lwsp
+}
+{
+ illegal 100 0 00000 00000 10 # c.jr, RES rs1=0
+ jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR
+ addi 100 0 ..... ..... 10 @c_mv
+}
+{
+ ebreak 100 1 00000 00000 10
+ jalr 100 1 ..... 00000 10 @c_jalr rd=1 # C.JALR
+ add 100 1 ..... ..... 10 @cr
+}
+fsd 101 ...... ..... 10 @c_sdsp
+sw 110 . ..... ..... 10 @c_swsp
%imm_u 12:s20 !function=ex_shift_12
# Argument sets:
+&empty
&b imm rs2 rs1
&i imm rs1 rd
+&j imm rd
&r rd rs1 rs2
+&s imm rs1 rs2
+&u imm rd
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
-@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
-@u .................... ..... ....... imm=%imm_u %rd
-@j .................... ..... ....... imm=%imm_j %rd
+@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
+@u .................... ..... ....... &u imm=%imm_u %rd
+@j .................... ..... ....... &j imm=%imm_j %rd
@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
@csr ............ ..... ... ..... ....... %csr %rs1 %rd
{
/* always generates U-level ECALL, fixed in do_interrupt handler */
generate_exception(ctx, RISCV_EXCP_U_ECALL);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
{
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
if (has_ext(ctx, RVS)) {
gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
} else {
return false;
#ifndef CONFIG_USER_ONLY
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
+ exit_tb(ctx); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
#else
+++ /dev/null
-/*
- * RISC-V translation routines for the RVC Compressed Instruction Set.
- *
- * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
- * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
- * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a)
-{
- if (a->nzuimm == 0) {
- /* Reserved in ISA */
- return false;
- }
- arg_addi arg = { .rd = a->rd, .rs1 = 2, .imm = a->nzuimm };
- return trans_addi(ctx, &arg);
-}
-
-static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a)
-{
- arg_fld arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
- return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a)
-{
- arg_lw arg = { .rd = a->rd, .rs1 = a->rs1, .imm = a->uimm };
- return trans_lw(ctx, &arg);
-}
-
-static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FLW ( RV32FC-only ) */
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- arg_c_lw tmp;
- decode_insn16_extract_cl_w(ctx, &tmp, ctx->opcode);
- arg_flw arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
- return trans_flw(ctx, &arg);
-#else
- /* C.LD ( RV64C/RV128C-only ) */
- arg_c_fld tmp;
- decode_insn16_extract_cl_d(ctx, &tmp, ctx->opcode);
- arg_ld arg = { .rd = tmp.rd, .rs1 = tmp.rs1, .imm = tmp.uimm };
- return trans_ld(ctx, &arg);
-#endif
-}
-
-static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a)
-{
- arg_fsd arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
- return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a)
-{
- arg_sw arg = { .rs1 = a->rs1, .rs2 = a->rs2, .imm = a->uimm };
- return trans_sw(ctx, &arg);
-}
-
-static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FSW ( RV32FC-only ) */
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
-
- arg_c_sw tmp;
- decode_insn16_extract_cs_w(ctx, &tmp, ctx->opcode);
- arg_fsw arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
- return trans_fsw(ctx, &arg);
-#else
- /* C.SD ( RV64C/RV128C-only ) */
- arg_c_fsd tmp;
- decode_insn16_extract_cs_d(ctx, &tmp, ctx->opcode);
- arg_sd arg = { .rs1 = tmp.rs1, .rs2 = tmp.rs2, .imm = tmp.uimm };
- return trans_sd(ctx, &arg);
-#endif
-}
-
-static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a)
-{
- if (a->imm == 0) {
- /* Hint: insn is valid but does not affect state */
- return true;
- }
- arg_addi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
- return trans_addi(ctx, &arg);
-}
-
-static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a)
-{
-#ifdef TARGET_RISCV32
- /* C.JAL */
- arg_c_j tmp;
- decode_insn16_extract_cj(ctx, &tmp, ctx->opcode);
- arg_jal arg = { .rd = 1, .imm = tmp.imm };
- return trans_jal(ctx, &arg);
-#else
- /* C.ADDIW */
- arg_addiw arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
- return trans_addiw(ctx, &arg);
-#endif
-}
-
-static bool trans_c_li(DisasContext *ctx, arg_c_li *a)
-{
- if (a->rd == 0) {
- /* Hint: insn is valid but does not affect state */
- return true;
- }
- arg_addi arg = { .rd = a->rd, .rs1 = 0, .imm = a->imm };
- return trans_addi(ctx, &arg);
-}
-
-static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a)
-{
- if (a->rd == 2) {
- /* C.ADDI16SP */
- arg_addi arg = { .rd = 2, .rs1 = 2, .imm = a->imm_addi16sp };
- return trans_addi(ctx, &arg);
- } else if (a->imm_lui != 0) {
- /* C.LUI */
- if (a->rd == 0) {
- /* Hint: insn is valid but does not affect state */
- return true;
- }
- arg_lui arg = { .rd = a->rd, .imm = a->imm_lui };
- return trans_lui(ctx, &arg);
- }
- return false;
-}
-
-static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a)
-{
- int shamt = a->shamt;
- if (shamt == 0) {
- /* For RV128 a shamt of 0 means a shift by 64 */
- shamt = 64;
- }
- /* Ensure, that shamt[5] is zero for RV32 */
- if (shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- arg_srli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
- return trans_srli(ctx, &arg);
-}
-
-static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a)
-{
- int shamt = a->shamt;
- if (shamt == 0) {
- /* For RV128 a shamt of 0 means a shift by 64 */
- shamt = 64;
- }
- /* Ensure, that shamt[5] is zero for RV32 */
- if (shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- arg_srai arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
- return trans_srai(ctx, &arg);
-}
-
-static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a)
-{
- arg_andi arg = { .rd = a->rd, .rs1 = a->rd, .imm = a->imm };
- return trans_andi(ctx, &arg);
-}
-
-static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a)
-{
- arg_sub arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_sub(ctx, &arg);
-}
-
-static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a)
-{
- arg_xor arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_xor(ctx, &arg);
-}
-
-static bool trans_c_or(DisasContext *ctx, arg_c_or *a)
-{
- arg_or arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_or(ctx, &arg);
-}
-
-static bool trans_c_and(DisasContext *ctx, arg_c_and *a)
-{
- arg_and arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_and(ctx, &arg);
-}
-
-static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a)
-{
-#ifdef TARGET_RISCV64
- arg_subw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_subw(ctx, &arg);
-#else
- return false;
-#endif
-}
-
-static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a)
-{
-#ifdef TARGET_RISCV64
- arg_addw arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_addw(ctx, &arg);
-#else
- return false;
-#endif
-}
-
-static bool trans_c_j(DisasContext *ctx, arg_c_j *a)
-{
- arg_jal arg = { .rd = 0, .imm = a->imm };
- return trans_jal(ctx, &arg);
-}
-
-static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a)
-{
- arg_beq arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
- return trans_beq(ctx, &arg);
-}
-
-static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a)
-{
- arg_bne arg = { .rs1 = a->rs1, .rs2 = 0, .imm = a->imm };
- return trans_bne(ctx, &arg);
-}
-
-static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a)
-{
- int shamt = a->shamt;
- if (shamt == 0) {
- /* For RV128 a shamt of 0 means a shift by 64 */
- shamt = 64;
- }
- /* Ensure, that shamt[5] is zero for RV32 */
- if (shamt >= TARGET_LONG_BITS) {
- return false;
- }
-
- arg_slli arg = { .rd = a->rd, .rs1 = a->rd, .shamt = a->shamt };
- return trans_slli(ctx, &arg);
-}
-
-static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a)
-{
- arg_fld arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
- return trans_fld(ctx, &arg);
-}
-
-static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a)
-{
- arg_lw arg = { .rd = a->rd, .rs1 = 2, .imm = a->uimm };
- return trans_lw(ctx, &arg);
-}
-
-static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FLWSP */
- arg_flw arg_flw = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_flwsp };
- return trans_flw(ctx, &arg_flw);
-#else
- /* C.LDSP */
- arg_ld arg_ld = { .rd = a->rd, .rs1 = 2, .imm = a->uimm_ldsp };
- return trans_ld(ctx, &arg_ld);
-#endif
- return false;
-}
-
-static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a)
-{
- if (a->rd != 0 && a->rs2 == 0) {
- /* C.JR */
- arg_jalr arg = { .rd = 0, .rs1 = a->rd, .imm = 0 };
- return trans_jalr(ctx, &arg);
- } else if (a->rd != 0 && a->rs2 != 0) {
- /* C.MV */
- arg_add arg = { .rd = a->rd, .rs1 = 0, .rs2 = a->rs2 };
- return trans_add(ctx, &arg);
- }
- return false;
-}
-
-static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_add *a)
-{
- if (a->rd == 0 && a->rs2 == 0) {
- /* C.EBREAK */
- arg_ebreak arg = { };
- return trans_ebreak(ctx, &arg);
- } else if (a->rd != 0) {
- if (a->rs2 == 0) {
- /* C.JALR */
- arg_jalr arg = { .rd = 1, .rs1 = a->rd, .imm = 0 };
- return trans_jalr(ctx, &arg);
- } else {
- /* C.ADD */
- arg_add arg = { .rd = a->rd, .rs1 = a->rd, .rs2 = a->rs2 };
- return trans_add(ctx, &arg);
- }
- }
- return false;
-}
-
-static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a)
-{
- arg_fsd arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
- return trans_fsd(ctx, &arg);
-}
-
-static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a)
-{
- arg_sw arg = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm };
- return trans_sw(ctx, &arg);
-}
-
-static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
-{
-#ifdef TARGET_RISCV32
- /* C.FSWSP */
- arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
- return trans_fsw(ctx, &a_fsw);
-#else
- /* C.SDSP */
- arg_sd a_sd = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_sdsp };
- return trans_sd(ctx, &a_sd);
-#endif
-}
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+static bool trans_illegal(DisasContext *ctx, arg_empty *a)
+{
+ gen_exception_illegal(ctx);
+ return true;
+}
+
static bool trans_lui(DisasContext *ctx, arg_lui *a)
{
if (a->rd != 0) {
if (a->rd != 0) {
tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
}
- tcg_gen_lookup_and_goto_ptr();
+ lookup_and_goto_ptr(ctx);
if (misaligned) {
gen_set_label(misaligned);
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
- return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
+ return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
}
static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
- return gen_arith_imm(ctx, a, &gen_slt);
+ return gen_arith_imm_tl(ctx, a, &gen_slt);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
- return gen_arith_imm(ctx, a, &gen_sltu);
+ return gen_arith_imm_tl(ctx, a, &gen_sltu);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
{
- return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
+ return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
}
static bool trans_ori(DisasContext *ctx, arg_ori *a)
{
- return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
+ return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
}
static bool trans_andi(DisasContext *ctx, arg_andi *a)
{
- return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
+ return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
#ifdef TARGET_RISCV64
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
- return gen_arith_imm(ctx, a, &gen_addw);
+ return gen_arith_imm_tl(ctx, a, &gen_addw);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
* however we need to end the translation block
*/
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- tcg_gen_exit_tb(NULL, 0);
+ exit_tb(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}
gen_io_end(); \
gen_set_gpr(a->rd, dest); \
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); \
- tcg_gen_exit_tb(NULL, 0); \
+ exit_tb(ctx); \
ctx->base.is_jmp = DISAS_NORETURN; \
tcg_temp_free(source1); \
tcg_temp_free(csr_store); \
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- if (env->priv == PRV_S &&
- env->priv_ver >= PRIV_VERSION_1_10_0 &&
- get_field(env->mstatus, MSTATUS_TVM)) {
+ if (!(env->priv >= PRV_S) ||
+ (env->priv == PRV_S &&
+ env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
tlb_flush(cs);
tcg_temp_free_i32(helper_tmp);
}
+/* Wrapper around tcg_gen_exit_tb that handles single stepping */
+static void exit_tb(DisasContext *ctx)
+{
+ if (ctx->base.singlestep_enabled) {
+ gen_exception_debug();
+ } else {
+ tcg_gen_exit_tb(NULL, 0);
+ }
+}
+
+/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
+static void lookup_and_goto_ptr(DisasContext *ctx)
+{
+ if (ctx->base.singlestep_enabled) {
+ gen_exception_debug();
+ } else {
+ tcg_gen_lookup_and_goto_ptr();
+ }
+}
+
static void gen_exception_illegal(DisasContext *ctx)
{
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
/* chaining is only allowed when the jump is to the same page */
tcg_gen_goto_tb(n);
tcg_gen_movi_tl(cpu_pc, dest);
+
+ /* No need to check for single stepping here as use_goto_tb() will
+ * return false in case of single stepping.
+ */
tcg_gen_exit_tb(ctx->base.tb, n);
} else {
tcg_gen_movi_tl(cpu_pc, dest);
- if (ctx->base.singlestep_enabled) {
- gen_exception_debug();
- } else {
- tcg_gen_lookup_and_goto_ptr();
- }
+ lookup_and_goto_ptr(ctx);
}
}
return 8 + reg;
}
-bool decode_insn32(DisasContext *ctx, uint32_t insn);
+static int ex_rvc_shifti(DisasContext *ctx, int imm)
+{
+ /* For RV128 a shamt of 0 means a shift by 64. */
+ return imm ? imm : 64;
+}
+
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
-static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
- void(*func)(TCGv, TCGv, TCGv))
+static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
+ void (*func)(TCGv, TCGv, target_long))
+{
+ TCGv source1;
+ source1 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+
+ (*func)(source1, source1, a->imm);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ return true;
+}
+
+static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
+ void (*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
#include "insn_trans/trans_rvd.inc.c"
#include "insn_trans/trans_privileged.inc.c"
-bool decode_insn16(DisasContext *ctx, uint16_t insn);
-/* auto-generated decoder*/
+/*
+ * Auto-generated decoder.
+ * Note that the 16-bit decoder reuses some of the trans_* functions
+ * initially declared by the 32-bit decoder, which results in duplicate
+ * declaration warnings. Suppress them.
+ */
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic push
+# pragma GCC diagnostic ignored "-Wredundant-decls"
+# ifdef __clang__
+# pragma GCC diagnostic ignored "-Wtypedef-redefinition"
+# endif
+#endif
+
#include "decode_insn16.inc.c"
-#include "insn_trans/trans_rvc.inc.c"
+
+#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE
+# pragma GCC diagnostic pop
+#endif
static void decode_opc(DisasContext *ctx)
{
#include "qemu/qemu-print.h"
#include "sysemu/sysemu.h"
#include "exec/cpu_ldst.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "exec/translator.h"
#include "exec/helper-proto.h"
#include "cpu.h"
#include "chardev/char-fe.h"
#include "exec/helper-proto.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "sysemu/sysemu.h"
--- /dev/null
+# Functional test that boots a VM and run commands via a SSH session
+#
+# Copyright (c) Philippe Mathieu-Daudé <f4bug@amsat.org>
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+import os
+import re
+import base64
+import logging
+import paramiko
+import time
+
+from avocado import skipIf
+from avocado_qemu import Test
+from avocado.utils import process
+from avocado.utils import archive
+
+
+class LinuxSSH(Test):
+
+ timeout = 150 # Not for 'configure --enable-debug --enable-debug-tcg'
+
+ KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
+ VM_IP = '127.0.0.1'
+
+ IMAGE_INFO = {
+ 'be': {
+ 'image_url': 'https://people.debian.org/~aurel32/qemu/mips/'
+ 'debian_wheezy_mips_standard.qcow2',
+ 'image_hash': '8987a63270df67345b2135a6b7a4885a35e392d5',
+ 'rsa_hostkey': b'AAAAB3NzaC1yc2EAAAADAQABAAABAQCca1VitiyLAdQOld'
+ b'zT43IOEVJZ0wHD78GJi8wDAjMiYWUzNSSn0rXGQsINHuH5'
+ b'IlF+kBZsHinb/FtKCAyS9a8uCHhQI4SuB4QhAb0+39MlUw'
+ b'Mm0CLkctgM2eUUZ6MQMQvDlqnue6CCkxN62EZYbaxmby7j'
+ b'CQa1125o1HRKBvdGm2zrJWxXAfA+f1v6jHLyE8Jnu83eQ+'
+ b'BFY25G+Vzx1PVc3zQBwJ8r0NGTRqy2//oWQP0h+bMsgeFe'
+ b'KH/J3RJM22vg6+I4JAdBFcxnK+l781h1FuRxOn4O/Xslbg'
+ b'go6WtB4V4TOsw2E/KfxI5IZ/icxF+swVcnvF46Hf3uQc/0'
+ b'BBqb',
+ },
+ 'le': {
+ 'image_url': 'https://people.debian.org/~aurel32/qemu/mipsel/'
+ 'debian_wheezy_mipsel_standard.qcow2',
+ 'image_hash': '7866764d9de3ef536ffca24c9fb9f04ffdb45802',
+ 'rsa_hostkey': b'AAAAB3NzaC1yc2EAAAADAQABAAABAQClXJlBT71HL5yKvv'
+ b'gfC7jmxSWx5zSBCzET6CLZczwAafSIs7YKfNOy/dQTxhuk'
+ b'yIGFUugZFoF3E9PzdhunuyvyTd56MPoNIqFbb5rGokwU5I'
+ b'TOx3dBHZR0mClypL6MVrwe0bsiIb8GhF1zioNwcsaAZnAi'
+ b'KfXStVDtXvn/kLLq+xLABYt48CC5KYWoFaCoICskLAY+qo'
+ b'L+LWyAnQisj4jAH8VSaSKIImFpfkHWEXPhHcC4ZBlDKtnH'
+ b'po9vhfCHgnfW3Pzrqmk8BI4HysqPFVmJWkJGlGUL+sGeg3'
+ b'ZZolAYuDXGuBrw8ooPJq2v2dOH+z6dyD2q/ypmAbyPqj5C'
+ b'rc8H',
+ },
+ }
+
+ def wait_for_console_pattern(self, success_message,
+ failure_message='Oops'):
+ console = self.vm.console_socket.makefile()
+ console_logger = logging.getLogger('console')
+ while True:
+ msg = console.readline()
+ console_logger.debug(msg.strip())
+ if success_message in msg:
+ break
+ if failure_message in msg:
+ fail = 'Failure message found in console: %s' % failure_message
+ self.fail(fail)
+
+ def get_portfwd(self):
+ res = self.vm.command('human-monitor-command',
+ command_line='info usernet')
+ line = res.split('\r\n')[2]
+ port = re.split(r'.*TCP.HOST_FORWARD.*127\.0\.0\.1 (\d+)\s+10\..*',
+ line)[1]
+ self.log.debug("sshd listening on port:" + port)
+ return port
+
+ def ssh_connect(self, username, password, rsa_hostkey_b64=None):
+ self.ssh_logger = logging.getLogger('ssh')
+ self.ssh_username = username
+ self.ssh_ps1 = '# ' if username is 'root' else '$ '
+ self.ssh_client = paramiko.SSHClient()
+ port = self.get_portfwd()
+ if rsa_hostkey_b64:
+ rsa_hostkey_bin = base64.b64decode(rsa_hostkey_b64)
+ rsa_hostkey = paramiko.RSAKey(data = rsa_hostkey_bin)
+ ipport = '[%s]:%s' % (self.VM_IP, port)
+ self.ssh_logger.debug('ipport ' + ipport)
+ self.ssh_client.get_host_keys().add(ipport, 'ssh-rsa', rsa_hostkey)
+ for i in range(10):
+ try:
+ self.ssh_client.connect(self.VM_IP, int(port),
+ username, password, banner_timeout=90)
+ self.ssh_logger.info("Entering interactive session.")
+ return
+ except:
+ time.sleep(4)
+ pass
+ self.fail("sshd timeout")
+
+ def ssh_disconnect_vm(self):
+ self.ssh_client.close()
+
+ def ssh_command(self, command, is_root=True):
+ self.ssh_logger.info(self.ssh_ps1 + command)
+ stdin, stdout, stderr = self.ssh_client.exec_command(command)
+ stdout_lines = [line.strip('\n') for line in stdout]
+ for line in stdout_lines:
+ self.ssh_logger.info(line)
+ stderr_lines = [line.strip('\n') for line in stderr]
+ for line in stderr_lines:
+ self.ssh_logger.warning(line)
+ return stdout_lines, stderr_lines
+
+ def boot_debian_wheezy_image_and_ssh_login(self, endianess, kernel_path):
+ image_url = self.IMAGE_INFO[endianess]['image_url']
+ image_hash = self.IMAGE_INFO[endianess]['image_hash']
+ image_path = self.fetch_asset(image_url, asset_hash=image_hash)
+ rsa_hostkey_b64 = self.IMAGE_INFO[endianess]['rsa_hostkey']
+
+ self.vm.set_machine('malta')
+ self.vm.set_console()
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE
+ + 'console=ttyS0 root=/dev/sda1')
+ self.vm.add_args('-no-reboot',
+ '-kernel', kernel_path,
+ '-append', kernel_command_line,
+ '-hda', image_path,
+ '-netdev', 'user,id=vnet,hostfwd=:127.0.0.1:0-:22',
+ '-device', 'pcnet,netdev=vnet')
+ self.vm.launch()
+
+ self.log.info('VM launched, waiting for sshd')
+ console_pattern = 'Starting OpenBSD Secure Shell server: sshd'
+ self.wait_for_console_pattern(console_pattern)
+ self.log.info('sshd ready')
+
+ self.ssh_connect('root', 'root', rsa_hostkey_b64=rsa_hostkey_b64)
+
+ def shutdown_via_ssh(self):
+ self.ssh_command('poweroff')
+ self.ssh_disconnect_vm()
+ self.wait_for_console_pattern('Power down')
+
+ def run_common_commands(self):
+ stdout, stderr = self.ssh_command('lspci -d 11ab:4620')
+ self.assertIn(True, ["GT-64120" in line for line in stdout])
+
+ stdout, stderr = self.ssh_command('cat /sys/bus/i2c/devices/i2c-0/name')
+ self.assertIn(True, ["SMBus PIIX4 adapter" in line
+ for line in stdout])
+
+ stdout, stderr = self.ssh_command('cat /proc/mtd')
+ self.assertIn(True, ["YAMON" in line
+ for line in stdout])
+
+ # Empty 'Board Config'
+ stdout, stderr = self.ssh_command('md5sum /dev/mtd2ro')
+ self.assertIn(True, ["0dfbe8aa4c20b52e1b8bf3cb6cbdf193" in line
+ for line in stdout])
+
+ def do_test_mips_malta(self, endianess, kernel_path, uname_m):
+ self.boot_debian_wheezy_image_and_ssh_login(endianess, kernel_path)
+
+ stdout, stderr = self.ssh_command('uname -a')
+ self.assertIn(True, [uname_m + " GNU/Linux" in line for line in stdout])
+
+ self.run_common_commands()
+ self.shutdown_via_ssh()
+
+ @skipIf(os.getenv('CONTINUOUS_INTEGRATION'), 'Running on Travis-CI')
+ def test_mips_malta32eb_kernel3_2_0(self):
+ """
+ :avocado: tags=arch:mips
+ :avocado: tags=machine:malta
+ :avocado: tags=endian:big
+ :avocado: tags=device:pcnet32
+ """
+ kernel_url = ('https://people.debian.org/~aurel32/qemu/mips/'
+ 'vmlinux-3.2.0-4-4kc-malta')
+ kernel_hash = '592e384a4edc16dade52a6cd5c785c637bcbc9ad'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+ self.do_test_mips_malta('be', kernel_path, 'mips')
+
+ @skipIf(os.getenv('CONTINUOUS_INTEGRATION'), 'Running on Travis-CI')
+ def test_mips_malta32el_kernel3_2_0(self):
+ """
+ :avocado: tags=arch:mipsel
+ :avocado: tags=machine:malta
+ :avocado: tags=endian:little
+ :avocado: tags=device:pcnet32
+ """
+ kernel_url = ('https://people.debian.org/~aurel32/qemu/mipsel/'
+ 'vmlinux-3.2.0-4-4kc-malta')
+ kernel_hash = 'a66bea5a8adaa2cb3d36a1d4e0ccdb01be8f6c2a'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+ self.do_test_mips_malta('le', kernel_path, 'mips')
+
+ @skipIf(os.getenv('CONTINUOUS_INTEGRATION'), 'Running on Travis-CI')
+ def test_mips_malta64eb_kernel3_2_0(self):
+ """
+ :avocado: tags=arch:mips64
+ :avocado: tags=machine:malta
+ :avocado: tags=endian:big
+ :avocado: tags=device:pcnet32
+ """
+ kernel_url = ('https://people.debian.org/~aurel32/qemu/mips/'
+ 'vmlinux-3.2.0-4-5kc-malta')
+ kernel_hash = 'db6eea7de35d36c77d8c165b6bcb222e16eb91db'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+ self.do_test_mips_malta('be', kernel_path, 'mips64')
+
+ @skipIf(os.getenv('CONTINUOUS_INTEGRATION'), 'Running on Travis-CI')
+ def test_mips_malta64el_kernel3_2_0(self):
+ """
+ :avocado: tags=arch:mips64el
+ :avocado: tags=machine:malta
+ :avocado: tags=endian:little
+ :avocado: tags=device:pcnet32
+ """
+ kernel_url = ('https://people.debian.org/~aurel32/qemu/mipsel/'
+ 'vmlinux-3.2.0-4-5kc-malta')
+ kernel_hash = '6a7f77245acf231415a0e8b725d91ed2f3487794'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+ self.do_test_mips_malta('le', kernel_path, 'mips64')
bzip2-devel \
ccache \
clang \
+ cyrus-sasl-devel \
device-mapper-multipath-devel \
findutils \
flex \
libaio-devel \
libasan \
libattr-devel \
+ libblockdev-mpath-devel \
libcap-devel \
libcap-ng-devel \
libcurl-devel \
libfdt-devel \
+ libiscsi-devel \
libjpeg-devel \
+ libpmem-devel \
libpng-devel \
librbd-devel \
+ libseccomp-devel \
libssh2-devel \
libubsan \
libusbx-devel \
pixman-devel \
python3 \
PyYAML \
+ rdma-core-devel \
SDL2-devel \
snappy-devel \
sparse \
spice-server-devel \
+ systemd-devel \
systemtap-sdt-devel \
tar \
usbredir-devel \
--- /dev/null
+FROM ubuntu:18.04
+ENV PACKAGES flex bison \
+ ccache \
+ clang \
+ gcc \
+ gettext \
+ git \
+ glusterfs-common \
+ libaio-dev \
+ libattr1-dev \
+ libbluetooth-dev \
+ libbrlapi-dev \
+ libbz2-dev \
+ libcacard-dev \
+ libcap-dev \
+ libcap-ng-dev \
+ libcurl4-gnutls-dev \
+ libdrm-dev \
+ libepoxy-dev \
+ libfdt-dev \
+ libgbm-dev \
+ libgtk-3-dev \
+ libibverbs-dev \
+ libiscsi-dev \
+ libjemalloc-dev \
+ libjpeg-turbo8-dev \
+ liblzo2-dev \
+ libncurses5-dev \
+ libncursesw5-dev \
+ libnfs-dev \
+ libnss3-dev \
+ libnuma-dev \
+ libpixman-1-dev \
+ librados-dev \
+ librbd-dev \
+ librdmacm-dev \
+ libsasl2-dev \
+ libsdl2-dev \
+ libseccomp-dev \
+ libsnappy-dev \
+ libspice-protocol-dev \
+ libspice-server-dev \
+ libssh2-1-dev \
+ libusb-1.0-0-dev \
+ libusbredirhost-dev \
+ libvdeplug-dev \
+ libvte-2.91-dev \
+ libxen-dev \
+ make \
+ python-yaml \
+ sparse \
+ texinfo \
+ xfslibs-dev
+RUN apt-get update && \
+ apt-get -y install $PACKAGES
+RUN dpkg -l $PACKAGES | sort > /packages.txt
+ENV FEATURES clang pyyaml sdl2
res = self.vm.qmp('query-block-jobs')
self.assert_qmp(res, 'return[0]/status', 'concluded')
# Leave zombie job un-dismissed, observe a failure:
- res = self.qmp_backup_and_wait(serror='Need a root block node',
+ res = self.qmp_backup_and_wait(serror="Node 'drive0' is busy: block device is in use by block job: backup",
device='drive0', format=iotests.imgfmt,
sync='full', target=self.dest_img,
auto_dismiss=False)
echo
echo "=== Testing overlap while COW is in flight ==="
echo
+BACKING_IMG=$TEST_IMG.base
+TEST_IMG=$BACKING_IMG _make_test_img 1G
+
+$QEMU_IO -c 'write 0k 64k' "$BACKING_IMG" | _filter_qemu_io
+
# compat=0.10 is required in order to make the following discard actually
# unallocate the sector rather than make it a zero sector - we want COW, after
# all.
-IMGOPTS='compat=0.10' _make_test_img 1G
+IMGOPTS='compat=0.10' _make_test_img -b "$BACKING_IMG" 1G
# Write two clusters, the second one enforces creation of an L2 table after
# the first data cluster.
$QEMU_IO -c 'write 0k 64k' -c 'write 512M 64k' "$TEST_IMG" | _filter_qemu_io
=== Testing overlap while COW is in flight ===
-Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824
+Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=1073741824
+wrote 65536/65536 bytes at offset 0
+64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
+Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 backing_file=TEST_DIR/t.IMGFMT.base
wrote 65536/65536 bytes at offset 0
64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec)
wrote 65536/65536 bytes at offset 536870912
--- /dev/null
+#!/usr/bin/env python
+#
+# Test external snapshot with bitmap copying.
+#
+# Copyright (c) 2019 Virtuozzo International GmbH. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+import iotests
+from iotests import qemu_img_create, file_path, log
+
+disk, top = file_path('disk', 'top')
+size = 1024 * 1024
+
+qemu_img_create('-f', iotests.imgfmt, disk, str(size))
+
+vm = iotests.VM().add_drive(disk, opts='node-name=base')
+vm.launch()
+
+vm.qmp_log('block-dirty-bitmap-add', node='drive0', name='bitmap0')
+
+vm.hmp_qemu_io('drive0', 'write 0 512K')
+
+vm.qmp_log('transaction', indent=2, actions=[
+ {'type': 'blockdev-snapshot-sync',
+ 'data': {'device': 'drive0', 'snapshot-file': top,
+ 'snapshot-node-name': 'snap'}},
+ {'type': 'block-dirty-bitmap-add',
+ 'data': {'node': 'snap', 'name': 'bitmap0'}},
+ {'type': 'block-dirty-bitmap-merge',
+ 'data': {'node': 'snap', 'target': 'bitmap0',
+ 'bitmaps': [{'node': 'base', 'name': 'bitmap0'}]}}
+], filters=[iotests.filter_qmp_testfiles])
+
+result = vm.qmp('query-block')['return'][0]
+log("query-block: device = {}, node-name = {}, dirty-bitmaps:".format(
+ result['device'], result['inserted']['node-name']))
+log(result['dirty-bitmaps'], indent=2)
+
+vm.shutdown()
--- /dev/null
+{"execute": "block-dirty-bitmap-add", "arguments": {"name": "bitmap0", "node": "drive0"}}
+{"return": {}}
+{
+ "execute": "transaction",
+ "arguments": {
+ "actions": [
+ {
+ "data": {
+ "device": "drive0",
+ "snapshot-file": "TEST_DIR/PID-top",
+ "snapshot-node-name": "snap"
+ },
+ "type": "blockdev-snapshot-sync"
+ },
+ {
+ "data": {
+ "name": "bitmap0",
+ "node": "snap"
+ },
+ "type": "block-dirty-bitmap-add"
+ },
+ {
+ "data": {
+ "bitmaps": [
+ {
+ "name": "bitmap0",
+ "node": "base"
+ }
+ ],
+ "node": "snap",
+ "target": "bitmap0"
+ },
+ "type": "block-dirty-bitmap-merge"
+ }
+ ]
+ }
+}
+{
+ "return": {}
+}
+query-block: device = drive0, node-name = snap, dirty-bitmaps:
+[
+ {
+ "busy": false,
+ "count": 524288,
+ "granularity": 65536,
+ "name": "bitmap0",
+ "persistent": false,
+ "recording": true,
+ "status": "active"
+ }
+]
notrun=""
casenotrun=""
interrupt=true
-
-# by default don't output timestamps
-timestamp=${TIMESTAMP:=false}
+makecheck=false
_init_error()
{
echo "$os/$platform $host $kernel"
}
+_full_env_details()
+{
+ cat <<EOF
+QEMU -- "$QEMU_PROG" $QEMU_OPTIONS
+QEMU_IMG -- "$QEMU_IMG_PROG" $QEMU_IMG_OPTIONS
+QEMU_IO -- "$QEMU_IO_PROG" $QEMU_IO_OPTIONS
+QEMU_NBD -- "$QEMU_NBD_PROG" $QEMU_NBD_OPTIONS
+IMGFMT -- $FULL_IMGFMT_DETAILS
+IMGPROTO -- $IMGPROTO
+PLATFORM -- $FULL_HOST_DETAILS
+TEST_DIR -- $TEST_DIR
+SOCKET_SCM_HELPER -- $SOCKET_SCM_HELPER
+
+EOF
+}
+
# $1 = prog to look for
set_prog_path()
{
-misalign misalign memory allocations
-n show me, do not run tests
-o options -o options to pass to qemu-img create/convert
- -T output timestamps
-c mode cache mode
+ -makecheck pretty print output for make check
testlist options
-g group[,group...] include tests from these groups
command -v xxdiff >/dev/null 2>&1 && diff=xxdiff
fi
;;
-
+ -makecheck) # makecheck friendly output
+ makecheck=true
+ xpand=false
+ ;;
-n) # show me, don't do it
showme=true
xpand=false
cachemode=true
xpand=false
;;
- -T) # turn on timestamp output
- timestamp=true
+ -T) # deprecated timestamp option
xpand=false
;;
date "+%H %M %S" | awk '{ print $1*3600 + $2*60 + $3 }'
}
-_timestamp()
-{
- now=$(date "+%T")
- printf %s " [$now]"
-}
-
_wrapup()
{
if $showme
trap "_wrapup; exit \$status" 0 1 2 3 15
+# Report the test start and results. For makecheck we want to pretty
+# print the whole report at the end of the execution.
+# args: $seq, $starttime, $lasttime
+_report_test_start()
+{
+ if ! $makecheck; then
+ if [ -n "$3" ]; then
+ local lasttime=" (last: $3s)"
+ fi
+ printf "%-8s %-10s [%s] %4s%-14s\r" "$1" "..." "$2" "..." "$lasttime"
+ fi
+}
+# args:$seq $status $starttime $lasttime $thistime $details
+_report_test_result()
+{
+ local status lasttime thistime
+ if $makecheck; then
+ if [ -n "$2" ] && [ "$2" != "pass" ]; then
+ status=" [$2]"
+ fi
+ printf " TEST iotest-$IMGFMT: %s%s\n" "$1" "$status"
+ return
+ fi
+
+ if [ -n "$4" ]; then
+ lasttime=" (last: $4s)"
+ fi
+ if [ -n "$5" ]; then
+ thistime=" $5s"
+ fi
+ case "$2" in
+ "pass") status=$(printf "\e[32m%-10s\e[0m" "$2") ;;
+ "fail") status=$(printf "\e[1m\e[31m%-10s\e[0m" "$2") ;;
+ "not run") status=$(printf "\e[33m%-10s\e[0m" "$2") ;;
+ *) status=$(printf "%-10s" "$2") ;;
+ esac
+
+ printf "%-8s %s [%s] [%s] %4s%-14s %s\n" "$1" "$status" "$3" "$(date '+%T')" "$thistime" "$lasttime" "$6"
+}
+
[ -f $TIMESTAMP_FILE ] || touch $TIMESTAMP_FILE
FULL_IMGFMT_DETAILS=$(_full_imgfmt_details)
FULL_HOST_DETAILS=$(_full_platform_details)
-cat <<EOF
-QEMU -- "$QEMU_PROG" $QEMU_OPTIONS
-QEMU_IMG -- "$QEMU_IMG_PROG" $QEMU_IMG_OPTIONS
-QEMU_IO -- "$QEMU_IO_PROG" $QEMU_IO_OPTIONS
-QEMU_NBD -- "$QEMU_NBD_PROG" $QEMU_NBD_OPTIONS
-IMGFMT -- $FULL_IMGFMT_DETAILS
-IMGPROTO -- $IMGPROTO
-PLATFORM -- $FULL_HOST_DETAILS
-TEST_DIR -- $TEST_DIR
-SOCKET_SCM_HELPER -- $SOCKET_SCM_HELPER
-
-EOF
+if ! $makecheck; then
+ _full_env_details
+fi
seq="check"
for seq in $list
do
- err=false
- printf %s "$seq"
+ err=false # error flag
+ printdiff=false # show diff to reference output?
+ status="" # test result summary
+ results="" # test result details
+
if [ -n "$TESTS_REMAINING_LOG" ] ; then
sed -e "s/$seq//" -e 's/ / /' -e 's/^ *//' $TESTS_REMAINING_LOG > $TESTS_REMAINING_LOG.tmp
mv $TESTS_REMAINING_LOG.tmp $TESTS_REMAINING_LOG
sync
fi
+ lasttime=$(sed -n -e "/^$seq /s/.* //p" <$TIMESTAMP_FILE)
+ starttime=$(date "+%T")
+ _report_test_start $seq $starttime $lasttime
+
if $showme
then
- echo
- continue
+ status="not run"
elif [ -f expunged ] && $expunge && egrep "^$seq([ ]|\$)" expunged >/dev/null
then
- echo " - expunged"
+ status="not run"
+ results="expunged"
rm -f $seq.out.bad
echo "/^$seq\$/d" >>$tmp.expunged
elif [ ! -f "$source_iotests/$seq" ]
then
- echo " - no such test?"
+ status="not run"
+ results="no such test?"
echo "/^$seq\$/d" >>$tmp.expunged
else
# really going to try and run this one
#
rm -f $seq.out.bad
- lasttime=$(sed -n -e "/^$seq /s/.* //p" <$TIMESTAMP_FILE)
- if [ "X$lasttime" != X ]; then
- printf %s " ${lasttime}s ..."
- else
- printf " " # prettier output with timestamps.
- fi
rm -f core $seq.notrun
rm -f $seq.casenotrun
start=$(_wallclock)
- $timestamp && printf %s " [$(date "+%T")]"
if [ "$(head -n 1 "$source_iotests/$seq")" == "#!/usr/bin/env python" ]; then
run_command="$PYTHON $seq"
$run_command >$tmp.out 2>&1)
fi
sts=$?
- $timestamp && _timestamp
stop=$(_wallclock)
if [ -f core ]
then
- printf " [dumped core]"
mv core $seq.core
+ status="fail"
+ results="[dumped core] $seq.core"
err=true
fi
if [ -f $seq.notrun ]
then
- $timestamp || printf " [not run] "
- $timestamp && echo " [not run]" && printf %s " $seq -- "
- cat $seq.notrun
- notrun="$notrun $seq"
+ # overwrites timestamp output
+ status="not run"
+ results="$(cat $seq.notrun)"
else
if [ $sts -ne 0 ]
then
- printf %s " [failed, exit status $sts]"
+ status="fail"
+ results=$(printf %s "[failed, exit status $sts]")
err=true
fi
if [ ! -f "$reference" ]
then
- echo " - no qualified output"
+ status="fail"
+ reason="no qualified output"
err=true
else
if diff -w "$reference" $tmp.out >/dev/null 2>&1
then
- echo ""
- if $err
- then
- :
- else
- echo "$seq $(expr $stop - $start)" >>$tmp.time
+ if ! $err; then
+ status="pass"
+ thistime=$(expr $stop - $start)
+ echo "$seq $thistime" >>$tmp.time
fi
else
- echo " - output mismatch (see $seq.out.bad)"
mv $tmp.out $seq.out.bad
$diff -w "$reference" "$PWD"/$seq.out.bad
+ status="fail"
+ results="output mismatch (see $seq.out.bad)"
+ printdiff=true
err=true
fi
fi
# come here for each test, except when $showme is true
#
- if $err
- then
- bad="$bad $seq"
- n_bad=$(expr $n_bad + 1)
- quick=false
- fi
- [ -f $seq.notrun ] || try=$(expr $try + 1)
+ _report_test_result $seq "$status" "$starttime" "$lasttime" "$thistime" "$results"
+ case "$status" in
+ "pass")
+ try=$(expr $try + 1)
+ ;;
+ "fail")
+ try=$(expr $try + 1)
+ if $makecheck; then
+ _full_env_details
+ fi
+ if $printdiff; then
+ $diff -w "$reference" "$PWD"/$seq.out.bad
+ fi
+ bad="$bad $seq"
+ n_bad=$(expr $n_bad + 1)
+ quick=false
+ ;;
+ "not run")
+ notrun="$notrun $seq"
+ ;;
+ esac
seq="after_$seq"
done
#
# QA groups control file
# Defines test groups
+#
+# Some notes about the groups:
+#
# - do not start group names with a digit
#
+# - quick : Tests in this group should finish within some few seconds.
+#
+# - img : Tests in this group can be used to excercise the qemu-img tool.
+#
+# - auto : Tests in this group are used during "make check" and should be
+# runnable in any case. That means they should run with every QEMU binary
+# (also non-x86), with every QEMU configuration (i.e. must not fail if
+# an optional feature is not compiled in - but reporting a "skip" is ok),
+# and work all kind of host filesystems and users (e.g. "nobody" or "root").
+#
#
# test-group association ... one line per test
023 rw auto
024 rw backing auto quick
025 rw auto quick
-026 rw blkdbg auto
+026 rw blkdbg
027 rw auto quick
-028 rw backing auto quick
+028 rw backing quick
029 rw auto quick
-030 rw auto backing
+030 rw backing
031 rw auto quick
032 rw auto quick
033 rw auto quick
037 rw auto backing quick
038 rw auto backing quick
039 rw auto quick
-040 rw auto
-041 rw auto backing
+040 rw
+041 rw backing
042 rw auto quick
043 rw auto backing
-044 rw auto
-045 rw auto quick
+044 rw
+045 rw quick
046 rw auto aio quick
047 rw auto quick
048 img auto quick
049 rw auto
050 rw auto backing quick
-051 rw auto
+051 rw
052 rw auto backing quick
053 rw auto quick
054 rw auto quick
-055 rw auto
-056 rw auto backing
-057 rw auto
-058 rw auto quick
+055 rw
+056 rw backing
+057 rw
+058 rw quick
059 rw auto quick
060 rw auto quick
061 rw auto
062 rw auto quick
063 rw auto quick
064 rw auto quick
-065 rw auto quick
+065 rw quick
066 rw auto quick
-067 rw auto quick
-068 rw auto quick
+067 rw quick
+068 rw quick
069 rw auto quick
070 rw auto quick
071 rw auto quick
082 rw auto quick
083 rw auto
084 img auto quick
-085 rw auto
+085 rw
086 rw auto quick
-087 rw auto quick
+087 rw quick
088 rw auto quick
089 rw auto quick
090 rw auto quick
091 rw auto migration
092 rw auto quick
-093 auto
+093 throttle
094 rw auto quick
-095 rw auto quick
-096 rw auto quick
+095 rw quick
+096 rw quick
097 rw auto backing
098 rw auto backing quick
099 rw auto quick
109 rw auto
110 rw auto backing quick
111 rw auto quick
-112 rw auto
+112 rw
113 rw auto quick
114 rw auto quick
-115 rw auto
+115 rw
116 rw auto quick
117 rw auto
-118 rw auto
+118 rw
119 rw auto quick
120 rw auto quick
-121 rw auto
+121 rw
122 rw auto
123 rw auto quick
-124 rw auto backing
-125 rw auto
+124 rw backing
+125 rw
126 rw auto backing
-127 rw auto backing quick
+127 rw backing quick
128 rw auto quick
-129 rw auto quick
+129 rw quick
130 rw auto quick
131 rw auto quick
-132 rw auto quick
+132 rw quick
133 auto quick
134 rw auto quick
135 rw auto
-136 rw auto
+136 rw
137 rw auto
138 rw auto quick
-139 rw auto quick
+139 rw quick
140 rw auto quick
141 rw auto quick
142 auto
143 auto quick
-144 rw auto quick
-145 auto quick
+144 rw quick
+145 quick
146 auto quick
-147 auto
-148 rw auto quick
-149 rw auto sudo
+147 img
+148 rw quick
+149 rw sudo
150 rw auto quick
-151 rw auto
-152 rw auto quick
-153 rw auto quick
+151 rw
+152 rw quick
+153 rw quick
154 rw auto backing quick
-155 rw auto
+155 rw
156 rw auto quick
-157 auto
+157 quick
158 rw auto quick
159 rw auto quick
160 rw auto quick
161 rw auto quick
-162 auto quick
-163 rw auto
-165 rw auto quick
-169 rw auto quick migration
+162 quick
+163 rw
+165 rw quick
+169 rw quick migration
170 rw auto quick
171 rw auto quick
172 auto
175 auto quick
176 rw auto backing
177 rw auto quick
-178 auto
+178 img
179 rw auto quick
181 rw auto migration
-182 rw auto quick
-183 rw auto migration
+182 rw quick
+183 rw migration
184 rw auto quick
-185 rw auto
+185 rw
186 rw auto
187 rw auto
-188 rw auto quick
-189 rw auto
+188 rw quick
+189 rw
190 rw auto quick
191 rw auto
192 rw auto quick
-194 rw auto migration quick
+194 rw migration quick
195 rw auto quick
-196 rw auto quick migration
+196 rw quick migration
197 rw auto quick
-198 rw auto
-199 rw auto migration
-200 rw auto
+198 rw
+199 rw migration
+200 rw
201 rw auto migration
-202 rw auto quick
-203 rw auto migration
-204 rw auto quick
-205 rw auto quick
-206 rw auto
+202 rw quick
+203 rw migration
+204 rw quick
+205 rw quick
+206 rw
207 rw auto
-208 rw auto quick
-209 rw auto quick
+208 rw quick
+209 rw quick
210 rw auto
211 rw auto quick
212 rw auto quick
213 rw auto quick
214 rw auto
215 rw auto quick
-216 rw auto quick
+216 rw quick
217 rw auto quick
-218 rw auto quick
-219 rw auto
+218 rw quick
+219 rw
220 rw auto
221 rw auto quick
-222 rw auto quick
-223 rw auto quick
-224 rw auto quick
+222 rw quick
+223 rw quick
+224 rw quick
225 rw auto quick
226 auto quick
-227 auto quick
-228 rw auto quick
+227 quick
+228 rw quick
229 auto quick
231 auto quick
-232 auto quick
+232 quick
233 auto quick
-234 auto quick migration
-235 auto quick
-236 auto quick
+234 quick migration
+235 quick
+236 quick
237 rw auto quick
-238 auto quick
+238 quick
239 rw auto quick
-240 auto quick
+240 quick
241 rw auto quick
-242 rw auto quick
+242 rw quick
243 rw auto quick
244 rw auto quick
-245 rw auto
-246 rw auto quick
-247 rw auto quick
-248 rw auto quick
+245 rw
+246 rw quick
+247 rw quick
+248 rw quick
249 rw auto quick
252 rw auto backing quick
253 rw auto quick
+254 rw auto backing quick
# in the tests/venv Python virtual environment. For more info,
# refer to: https://pip.pypa.io/en/stable/user_guide/#id1
avocado-framework==68.0
+paramiko
# build options for bare programs are usually pretty different. They
# are expected to provide their own build recipes.
-include $(SRC_PATH)/tests/tcg/minilib/Makefile.target
+-include $(SRC_PATH)/tests/tcg/multiarch/system/Makefile.softmmu-target
-include $(SRC_PATH)/tests/tcg/$(TARGET_BASE_ARCH)/Makefile.softmmu-target
ifneq ($(TARGET_BASE_ARCH),$(TARGET_NAME))
-include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.softmmu-target
--- /dev/null
+#
+# Aarch64 system tests
+#
+
+AARCH64_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/aarch64/system
+VPATH+=$(AARCH64_SYSTEM_SRC)
+
+# These objects provide the basic boot code and helper functions for all tests
+CRT_OBJS=boot.o
+
+AARCH64_TEST_SRCS=$(wildcard $(AARCH64_SYSTEM_SRC)/*.c)
+AARCH64_TESTS = $(patsubst $(AARCH64_SYSTEM_SRC)/%.c, %, $(AARCH64_TEST_SRCS))
+
+CRT_PATH=$(AARCH64_SYSTEM_SRC)
+LINK_SCRIPT=$(AARCH64_SYSTEM_SRC)/kernel.ld
+LDFLAGS=-Wl,-T$(LINK_SCRIPT)
+TESTS+=$(AARCH64_TESTS) $(MULTIARCH_TESTS)
+CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC)
+LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc
+
+# building head blobs
+.PRECIOUS: $(CRT_OBJS)
+
+%.o: $(CRT_PATH)/%.S
+ $(CC) $(CFLAGS) -x assembler-with-cpp -c $< -o $@
+
+# Build and link the tests
+%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
+ $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)
+
+memory: CFLAGS+=-DCHECK_UNALIGNED=1
+
+# Running
+QEMU_OPTS+=-M virt -cpu max -display none -semihosting-config enable=on,target=native,chardev=output -kernel
--- /dev/null
+/*
+ * Minimal AArch64 system boot code.
+ *
+ * Copyright Linaro Ltd 2019
+ *
+ * Loosely based on the newlib/libgloss setup stubs. Using semihosting
+ * for serial output and exit functions.
+ */
+
+/*
+ * Semihosting interface on ARM AArch64
+ * See "Semihosting for AArch32 and AArch64 Relase 2.0" by ARM
+ * w0 - semihosting call number
+ * x1 - semihosting parameter
+ */
+#define semihosting_call hlt 0xf000
+#define SYS_WRITEC 0x03 /* character to debug channel */
+#define SYS_WRITE0 0x04 /* string to debug channel */
+#define SYS_EXIT 0x18
+
+ .align 12
+
+ .macro ventry label
+ .align 7
+ b \label
+ .endm
+
+vector_table:
+ /* Current EL with SP0. */
+ ventry curr_sp0_sync /* Synchronous */
+ ventry curr_sp0_irq /* Irq/vIRQ */
+ ventry curr_sp0_fiq /* Fiq/vFIQ */
+ ventry curr_sp0_serror /* SError/VSError */
+
+ /* Current EL with SPx. */
+ ventry curr_spx_sync /* Synchronous */
+ ventry curr_spx_irq /* IRQ/vIRQ */
+ ventry curr_spx_fiq /* FIQ/vFIQ */
+ ventry curr_spx_serror /* SError/VSError */
+
+ /* Lower EL using AArch64. */
+ ventry lower_a64_sync /* Synchronous */
+ ventry lower_a64_irq /* IRQ/vIRQ */
+ ventry lower_a64_fiq /* FIQ/vFIQ */
+ ventry lower_a64_serror /* SError/VSError */
+
+ /* Lower EL using AArch32. */
+ ventry lower_a32_sync /* Synchronous */
+ ventry lower_a32_irq /* IRQ/vIRQ */
+ ventry lower_a32_fiq /* FIQ/vFIQ */
+ ventry lower_a32_serror /* SError/VSError */
+
+ .text
+ .align 4
+
+ /* Common vector handling for now */
+curr_sp0_sync:
+curr_sp0_irq:
+curr_sp0_fiq:
+curr_sp0_serror:
+curr_spx_sync:
+curr_spx_irq:
+curr_spx_fiq:
+curr_spx_serror:
+lower_a64_sync:
+lower_a64_irq:
+lower_a64_fiq:
+lower_a64_serror:
+lower_a32_sync:
+lower_a32_irq:
+lower_a32_fiq:
+lower_a32_serror:
+ mov x0, SYS_WRITE0
+ adr x1, .error
+ semihosting_call
+ mov x0, SYS_EXIT
+ mov x1, 1
+ semihosting_call
+ /* never returns */
+
+ .section .rodata
+.error:
+ .string "Terminated by exception.\n"
+
+ .text
+ .align 4
+ .global __start
+__start:
+ /* Installs a table of exception vectors to catch and handle all
+ exceptions by terminating the process with a diagnostic. */
+ adr x0, vector_table
+ msr vbar_el1, x0
+
+ /* Page table setup (identity mapping). */
+ adrp x0, ttb
+ add x0, x0, :lo12:ttb
+ msr ttbr0_el1, x0
+
+ /*
+ * Setup a flat address mapping page-tables. Stage one simply
+ * maps RAM to the first Gb. The stage2 tables have two 2mb
+ * translation block entries covering a series of adjacent
+ * 4k pages.
+ */
+
+ /* Stage 1 entry: indexed by IA[38:30] */
+ adr x1, . /* phys address */
+ bic x1, x1, #(1 << 30) - 1 /* 1GB alignment*/
+ add x2, x0, x1, lsr #(30 - 3) /* offset in l1 page table */
+
+ /* point to stage 2 table [47:12] */
+ adrp x0, ttb_stage2
+ orr x1, x0, #3 /* ptr to stage 2 */
+ str x1, [x2]
+
+ /* Stage 2 entries: indexed by IA[29:21] */
+ ldr x5, =(((1 << 9) - 1) << 21)
+
+ /* First block: .text/RO/execute enabled */
+ adr x1, . /* phys address */
+ bic x1, x1, #(1 << 21) - 1 /* 2mb block alignment */
+ and x4, x1, x5 /* IA[29:21] */
+ add x2, x0, x4, lsr #(21 - 3) /* offset in l2 page table */
+ ldr x3, =0x401 /* attr(AF, block) */
+ orr x1, x1, x3
+ str x1, [x2] /* 1st 2mb (.text & rodata) */
+
+ /* Second block: .data/RW/no execute */
+ adrp x1, .data
+ add x1, x1, :lo12:.data
+ bic x1, x1, #(1 << 21) - 1 /* 2mb block alignment */
+ and x4, x1, x5 /* IA[29:21] */
+ add x2, x0, x4, lsr #(21 - 3) /* offset in l2 page table */
+ ldr x3, =(3 << 53) | 0x401 /* attr(AF, NX, block) */
+ orr x1, x1, x3
+ str x1, [x2] /* 2nd 2mb (.data & .bss)*/
+
+ /* Setup/enable the MMU. */
+
+ /*
+ * TCR_EL1 - Translation Control Registers
+ *
+ * IPS[34:32] = 40-bit PA, 1TB
+ * TG0[14:15] = b00 => 4kb granuale
+ * ORGN0[11:10] = Outer: Normal, WB Read-Alloc No Write-Alloc Cacheable
+ * IRGN0[9:8] = Inner: Normal, WB Read-Alloc No Write-Alloc Cacheable
+ * T0SZ[5:0] = 2^(64 - 25)
+ *
+ * The size of T0SZ controls what the initial lookup level. It
+ * would be nice to start at level 2 but unfortunatly for a
+ * flat-mapping on the virt machine we need to handle IA's
+ * with at least 1gb range to see RAM. So we start with a
+ * level 1 lookup.
+ */
+ ldr x0, = (2 << 32) | 25 | (3 << 10) | (3 << 8)
+ msr tcr_el1, x0
+
+ mov x0, #0xee /* Inner/outer cacheable WB */
+ msr mair_el1, x0
+ isb
+
+ /*
+ * SCTLR_EL1 - System Control Register
+ *
+ * WXN[19] = 0 = no effect, Write does not imply XN (execute never)
+ * I[12] = Instruction cachability control
+ * SA[3] = SP alignment check
+ * C[2] = Data cachability control
+ * M[0] = 1, enable stage 1 address translation for EL0/1
+ */
+ mrs x0, sctlr_el1
+ ldr x1, =0x100d /* bits I(12) SA(3) C(2) M(0) */
+ bic x0, x0, #(1 << 1) /* clear bit A(1) */
+ bic x0, x0, #(1 << 19) /* clear WXN */
+ orr x0, x0, x1 /* set bits */
+
+ dsb sy
+ msr sctlr_el1, x0
+ isb
+
+ /*
+ * Enable FP registers. The standard C pre-amble will be
+ * saving these and A-profile compilers will use AdvSIMD
+ * registers unless we tell it not to.
+ */
+ mrs x0, cpacr_el1
+ orr x0, x0, #(3 << 20)
+ msr cpacr_el1, x0
+
+ /* Setup some stack space and enter the test code.
+ * Assume everthing except the return value is garbage when we
+ * return, we won't need it.
+ */
+ adrp x0, stack_end
+ add x0, x0, :lo12:stack_end
+ mov sp, x0
+ bl main
+
+ /* pass return value to sys exit */
+ mov x1, x0
+ ldr x0, =0x20026 /* ADP_Stopped_ApplicationExit */
+ stp x0, x1, [sp, #-16]!
+ mov x1, sp
+ mov x0, SYS_EXIT
+ semihosting_call
+ /* never returns */
+
+ /*
+ * Helper Functions
+ */
+
+ /* Output a single character to serial port */
+ .global __sys_outc
+__sys_outc:
+ stp x0, x1, [sp, #-16]!
+ /* pass address of c on stack */
+ mov x1, sp
+ mov x0, SYS_WRITEC
+ semihosting_call
+ ldp x0, x1, [sp], #16
+ ret
+
+ .data
+ .align 12
+
+ /* Translation table
+ * @4k granuale: 9 bit lookup, 512 entries
+ */
+ttb:
+ .space 4096, 0
+
+ .align 12
+ttb_stage2:
+ .space 4096, 0
+
+ .align 12
+stack:
+ .space 65536, 0
+stack_end:
--- /dev/null
+ENTRY(__start)
+
+SECTIONS
+{
+ /* virt machine, RAM starts at 1gb */
+ . = (1 << 30);
+ .text : {
+ *(.text)
+ }
+ .rodata : {
+ *(.rodata)
+ }
+ /* align r/w section to next 2mb */
+ . = ALIGN(1 << 21);
+ .data : {
+ *(.data)
+ }
+ .bss : {
+ *(.bss)
+ }
+ /DISCARD/ : {
+ *(.ARM.attributes)
+ }
+}
--- /dev/null
+#
+# Alpha system tests
+#
+
+ALPHA_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/alpha/system
+VPATH+=$(ALPHA_SYSTEM_SRC)
+
+# These objects provide the basic boot code and helper functions for all tests
+CRT_OBJS=boot.o
+
+ALPHA_TEST_SRCS=$(wildcard $(ALPHA_SYSTEM_SRC)/*.c)
+ALPHA_TESTS = $(patsubst $(ALPHA_SYSTEM_SRC)/%.c, %, $(ALPHA_TEST_SRCS))
+
+CRT_PATH=$(ALPHA_SYSTEM_SRC)
+LINK_SCRIPT=$(ALPHA_SYSTEM_SRC)/kernel.ld
+LDFLAGS=-Wl,-T$(LINK_SCRIPT)
+TESTS+=$(ALPHA_TESTS) $(MULTIARCH_TESTS)
+CFLAGS+=-nostdlib -g -O1 -mcpu=ev6 $(MINILIB_INC)
+LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc
+
+# building head blobs
+.PRECIOUS: $(CRT_OBJS)
+
+%.o: $(CRT_PATH)/%.S
+ $(CC) $(CFLAGS) -x assembler-with-cpp -c $< -o $@
+
+# Build and link the tests
+%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
+ $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)
+
+memory: CFLAGS+=-DCHECK_UNALIGNED=0
+
+# Running
+QEMU_OPTS+=-serial chardev:output -kernel
--- /dev/null
+/*
+ * Minimal Alpha system boot code.
+ *
+ * Copyright Linaro Ltd 2019
+ */
+
+ .set noat
+ .set nomacro
+ .arch ev6
+ .text
+
+.macro load_pci_io reg
+ /* For typhoon, this is
+ * 0xfffffc0000000000 -- kseg identity map
+ * + 0x10000000000 -- typhoon pio base
+ * + 0x1fc000000 -- typhoon pchip0 pci base
+ * = 0xfffffd01fc000000
+ */
+ ldah \reg, -3 /* ff..fd0000 */
+ lda \reg, 0x1fc(\reg) /* ff..fd01fc */
+ sll \reg, 24, \reg
+.endm
+
+#define com1Rbr 0x3f8
+#define com1Thr 0x3f8
+#define com1Ier 0x3f9
+#define com1Iir 0x3fa
+#define com1Lcr 0x3fb
+#define com1Mcr 0x3fc
+#define com1Lsr 0x3fd
+#define com1Msr 0x3fe
+#define com1Scr 0x3ff
+#define com1Dll 0x3f8
+#define com1Dlm 0x3f9
+
+#define PAL_halt 0
+#define PAL_wrent 52
+#define PAL_wrkgp 55
+
+ .text
+ .p2align 4
+ .globl _start
+ .ent _start
+_start:
+ br $gp, .+4
+ ldah $gp, 0($gp) !gpdisp!1
+ lda $gp, 0($gp) !gpdisp!1
+
+ ldah $sp, $stack_end($gp) !gprelhigh
+ lda $sp, $stack_end($sp) !gprellow
+
+ /* Install kernel gp for exception handlers. */
+ mov $gp, $16
+ call_pal PAL_wrkgp
+
+ /* Install exception handlers. */
+ ldah $16, entInt($gp) !gprelhigh
+ lda $16, entInt($16) !gprellow
+ lda $17, 0
+ call_pal PAL_wrent
+
+ ldah $16, entArith($gp) !gprelhigh
+ lda $16, entArith($16) !gprellow
+ lda $17, 1
+ call_pal PAL_wrent
+
+ ldah $16, entMM($gp) !gprelhigh
+ lda $16, entMM($16) !gprellow
+ lda $17, 2
+ call_pal PAL_wrent
+
+ ldah $16, entIF($gp) !gprelhigh
+ lda $16, entIF($16) !gprellow
+ lda $17, 3
+ call_pal PAL_wrent
+
+ ldah $16, entUna($gp) !gprelhigh
+ lda $16, entUna($16) !gprellow
+ lda $17, 4
+ call_pal PAL_wrent
+
+ ldah $16, entSys($gp) !gprelhigh
+ lda $16, entSys($16) !gprellow
+ lda $17, 5
+ call_pal PAL_wrent
+
+ /*
+ * Initialize COM1.
+ */
+ load_pci_io $1
+ lda $2, 0x87 /* outb(0x87, com1Lcr); */
+ stb $2, com1Lcr($1)
+ stb $31, com1Dlm($1) /* outb(0, com1Dlm); */
+ lda $2, 3 /* baudconst 3 => 56000 */
+ stb $2, com1Dll($1) /* outb(baudconst, com1Dll); */
+ lda $2, 0x07
+ stb $2, com1Lcr($1) /* outb(0x07, com1Lcr) */
+ lda $2, 0x0f
+ stb $2, com1Mcr($1) /* outb(0x0f, com1Mcr) */
+
+ bsr $26, main !samegp
+
+ /* fall through to _exit */
+ .end _start
+
+ .globl _exit
+ .ent _exit
+_exit:
+ .frame $sp, 0, $26, 0
+ .prologue 0
+
+ /* We cannot return an error code. */
+ call_pal PAL_halt
+ .end _exit
+
+/*
+ * We have received an exception that we don't handle. Log and exit.
+ */
+ .ent log_exit
+log_exit:
+entInt:
+entArith:
+entMM:
+entIF:
+entUna:
+entSys:
+ ldah $16, $errormsg($gp) !gprelhigh
+ lda $16, $errormsg($16) !gprellow
+ bsr $26, __sys_outs !samegp
+ bsr $26, _exit !samegp
+ .end log_exit
+
+ .section .rodata
+$errormsg:
+ .string "Terminated by exception.\n"
+ .previous
+
+ /*
+ * Helper Functions
+ */
+
+ /* Output a single character to serial port */
+ .global __sys_outc
+ .ent __sys_outc
+__sys_outc:
+ .frame $sp, 0, $26, 0
+ .prologue 0
+
+ load_pci_io $1
+
+ /*
+ * while ((inb(com1Lsr) & 0x20) == 0)
+ * continue;
+ */
+1: ldbu $0, com1Lsr($1)
+ and $0, 0x20, $0
+ beq $0, 1b
+
+ /* outb(c, com1Thr); */
+ stb $16, com1Thr($1)
+ ret
+ .end __sys_outc
+
+ /* Output a nul-terminated string to serial port */
+ .global __sys_outs
+ .ent __sys_outs
+__sys_outs:
+ .frame $sp, 0, $26, 0
+ .prologue 0
+
+ load_pci_io $1
+
+ ldbu $2, 0($16)
+ beq $2, 9f
+
+ /*
+ * while ((inb(com1Lsr) & 0x20) == 0)
+ * continue;
+ */
+1: ldbu $0, com1Lsr($1)
+ and $0, 0x20, $0
+ beq $0, 1b
+
+ /* outb(c, com1Thr); */
+ stb $2, com1Thr($1)
+
+ addq $16, 1, $16
+ ldbu $2, 0($16)
+ bne $2, 1b
+
+9: ret
+ .end __sys_outs
+
+/*
+ * Division routines that are normally in libc.
+ *
+ * These do not follow the C calling convention. Arguments are in $24+$25,
+ * the result is in $27. Register $28 may be clobbered; everything else
+ * must be saved.
+ *
+ * We store the remainder in $28, so that we can share code.
+ *
+ * We do not signal divide by zero.
+ */
+
+/*
+ * Unsigned 64-bit division.
+ */
+
+ .globl __divqu
+ .ent __divqu
+__divqu:
+ .frame $sp, 48, $23
+ subq $sp, 48, $sp
+ stq $0, 0($sp)
+ stq $1, 8($sp)
+ stq $2, 16($sp)
+ stq $3, 24($sp)
+ stq $4, 32($sp)
+ .prologue 0
+
+#define mask $0
+#define divisor $1
+#define compare $2
+#define tmp1 $3
+#define tmp2 $4
+#define quotient $27
+#define modulus $28
+
+ mov $24, modulus
+ mov $25, divisor
+ mov $31, quotient
+ mov 1, mask
+ beq $25, 9f
+
+ /* Shift left until divisor >= modulus. */
+1: cmpult divisor, modulus, compare
+ blt divisor, 2f
+ addq divisor, divisor, divisor
+ addq mask, mask, mask
+ bne compare, 1b
+
+2: addq quotient, mask, tmp2
+ srl mask, 1, mask
+ cmpule divisor, modulus, compare
+ subq modulus, divisor, tmp1
+ cmovne compare, tmp2, quotient
+ srl divisor, 1, divisor
+ cmovne compare, tmp1, modulus
+ bne mask, 2b
+
+9: ldq $0, 0($sp)
+ ldq $1, 8($sp)
+ ldq $2, 16($sp)
+ ldq $3, 24($sp)
+ ldq $4, 32($sp)
+ addq $sp, 48, $sp
+ ret $31, ($23), 1
+
+#undef mask
+#undef divisor
+#undef compare
+#undef tmp1
+#undef tmp2
+#undef quotient
+#undef modulus
+
+ .end __divqu
+
+/*
+ * Unsigned 64-bit remainder.
+ * Note that __divqu above leaves the result in $28.
+ */
+
+ .globl __remqu
+ .ent __remqu
+__remqu:
+ .frame $sp, 16, $23
+ subq $sp, 16, $sp
+ stq $23, 0($sp)
+ .prologue 0
+
+ bsr $23, __divqu
+
+ ldq $23, 0($sp)
+ mov $28, $27
+ addq $sp, 16, $sp
+ ret $31, ($23), 1
+ .end __remqu
+
+/*
+ * Signed 64-bit division.
+ */
+
+ .globl __divqs
+ .ent __divqs
+__divqs:
+ .prologue 0
+
+ /* Common case: both arguments are positive. */
+ bis $24, $25, $28
+ bge $28, __divqu
+
+ /* At least one argument is negative. */
+ subq $sp, 32, $sp
+ stq $23, 0($sp)
+ stq $24, 8($sp)
+ stq $25, 16($sp)
+
+ /* Compute absolute values. */
+ subq $31, $24, $28
+ cmovlt $24, $28, $24
+ subq $31, $25, $28
+ cmovlt $25, $28, $25
+
+ bsr $23, __divqu
+
+ ldq $24, 8($sp)
+ ldq $25, 16($sp)
+
+ /* -a / b = a / -b = -(a / b) */
+ subq $31, $27, $23
+ xor $24, $25, $28
+ cmovlt $28, $23, $27
+
+ ldq $23, 0($sp)
+ addq $sp, 32, $sp
+ ret $31, ($23), 1
+ .end __divqs
+
+/*
+ * Signed 64-bit remainder.
+ */
+
+ .globl __remqs
+ .ent __remqs
+__remqs:
+ .prologue 0
+
+ /* Common case: both arguments are positive. */
+ bis $24, $25, $28
+ bge $28, __remqu
+
+ /* At least one argument is negative. */
+ subq $sp, 32, $sp
+ stq $23, 0($sp)
+ stq $24, 8($sp)
+ stq $25, 16($sp)
+
+ /* Compute absolute values. */
+ subq $31, $24, $28
+ cmovlt $24, $28, $24
+ subq $31, $25, $28
+ cmovlt $25, $28, $25
+
+ bsr $23, __divqu
+
+ ldq $23, 0($sp)
+ ldq $24, 8($sp)
+ ldq $25, 16($sp)
+
+ /* -a % b = -(a % b); a % -b = a % b. */
+ subq $31, $28, $27
+ cmovge $24, $28, $27
+
+ addq $sp, 32, $sp
+ ret $31, ($23), 1
+ .end __remqs
+
+/*
+ * Unsigned 32-bit division.
+ */
+
+ .globl __divlu
+ .ent __divlu
+__divlu:
+ .frame $sp, 32, $23
+ subq $sp, 32, $sp
+ stq $23, 0($sp)
+ stq $24, 8($sp)
+ stq $25, 16($sp)
+ .prologue 0
+
+ /* Zero extend and use the 64-bit routine. */
+ zap $24, 0xf0, $24
+ zap $25, 0xf0, $25
+ bsr $23, __divqu
+
+ addl $27, 0, $27
+ ldq $23, 0($sp)
+ ldq $24, 8($sp)
+ ldq $25, 16($sp)
+ addq $sp, 32, $sp
+ ret $31, ($23), 1
+ .end __divlu
+
+/*
+ * Unsigned 32-bit remainder.
+ */
+
+ .globl __remlu
+ .ent __remlu
+__remlu:
+ .frame $sp, 32, $23
+ subq $sp, 32, $sp
+ stq $23, 0($sp)
+ stq $24, 8($sp)
+ stq $25, 16($sp)
+ .prologue 0
+
+ /* Zero extend and use the 64-bit routine. */
+ zap $24, 0xf0, $24
+ zap $25, 0xf0, $25
+ bsr $23, __divqu
+
+ /* Recall that the remainder is returned in $28. */
+ addl $28, 0, $27
+ ldq $23, 0($sp)
+ ldq $24, 8($sp)
+ ldq $25, 16($sp)
+ addq $sp, 32, $sp
+ ret $31, ($23), 1
+ .end __remlu
+
+/*
+ * Signed 32-bit division.
+ */
+
+ .globl __divls
+ .ent __divls
+__divls:
+ .frame $sp, 32, $23
+ subq $sp, 32, $sp
+ stq $23, 0($sp)
+ stq $24, 8($sp)
+ stq $25, 16($sp)
+ .prologue 0
+
+ /* Sign extend. */
+ addl $24, 0, $24
+ addl $25, 0, $25
+
+ /* Compute absolute values. */
+ subq $31, $24, $28
+ cmovlt $24, $28, $24
+ subq $31, $25, $28
+ cmovlt $25, $28, $25
+
+ bsr $23, __divqu
+
+ ldq $24, 8($sp)
+ ldq $25, 16($sp)
+
+ /* Negate the unsigned result, if necessary. */
+ xor $24, $25, $28
+ subl $31, $27, $23
+ addl $27, 0, $27
+ addl $28, 0, $28
+ cmovlt $28, $23, $27
+
+ ldq $23, 0($sp)
+ addq $sp, 32, $sp
+ ret $31, ($23), 1
+ .end __divls
+
+/*
+ * Signed 32-bit remainder.
+ */
+
+ .globl __remls
+ .ent __remls
+__remls:
+ .frame $sp, 32, $23
+ subq $sp, 32, $sp
+ stq $23, 0($sp)
+ stq $24, 8($sp)
+ stq $25, 16($sp)
+ .prologue 0
+
+ /* Sign extend. */
+ addl $24, 0, $24
+ addl $25, 0, $25
+
+ /* Compute absolute values. */
+ subq $31, $24, $28
+ cmovlt $24, $28, $24
+ subq $31, $25, $28
+ cmovlt $25, $28, $25
+
+ bsr $23, __divqu
+
+ ldq $23, 0($sp)
+ ldq $24, 8($sp)
+ ldq $25, 16($sp)
+
+ /* Negate the unsigned result, if necessary. */
+ subl $31, $28, $27
+ addl $28, 0, $28
+ cmovge $24, $28, $27
+
+ addq $sp, 32, $sp
+ ret $31, ($23), 1
+ .end __remls
+
+ .data
+ .p2align 4
+stack:
+ .skip 65536
+$stack_end:
+ .type stack,@object
+ .size stack, . - stack
--- /dev/null
+ENTRY(_start)
+
+SECTIONS
+{
+ /* Linux kernel legacy start address. */
+ . = 0xfffffc0000310000;
+ _text = .;
+ .text : {
+ *(.text)
+ }
+ .rodata : {
+ *(.rodata)
+ }
+ _etext = .;
+
+ . = ALIGN(8192);
+ _data = .;
+ .got : {
+ *(.got)
+ }
+ .data : {
+ *(.sdata)
+ *(.data)
+ }
+ _edata = .;
+ .bss : {
+ *(.bss)
+ }
+ _end = .;
+}
LINK_SCRIPT=$(I386_SYSTEM_SRC)/kernel.ld
LDFLAGS=-Wl,-T$(LINK_SCRIPT) -Wl,-melf_i386
# FIXME: move to common once x86_64 is bootstrapped
-TESTS+=$(X86_TESTS)
+TESTS+=$(X86_TESTS) $(MULTIARCH_TESTS)
endif
CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC)
LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc
%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
$(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)
+memory: CFLAGS+=-DCHECK_UNALIGNED=1
+
# Running
QEMU_OPTS+=-device isa-debugcon,chardev=output -device isa-debug-exit,iobase=0xf4,iosize=0x4 -kernel
+++ /dev/null
-/*
- * Memory Test
- *
- * This is intended to test the softmmu code and ensure we properly
- * behave across normal and unaligned accesses across several pages.
- * We are not replicating memory tests for stuck bits and other
- * hardware level failures but looking for issues with different size
- * accesses when:
-
- *
- */
-
-#include <inttypes.h>
-#include <minilib.h>
-
-#define TEST_SIZE (4096 * 4) /* 4 pages */
-
-static uint8_t test_data[TEST_SIZE];
-
-static void pdot(int count)
-{
- if (count % 128 == 0) {
- ml_printf(".");
- }
-}
-
-
-/*
- * Fill the data with ascending value bytes. As x86 is a LE machine we
- * write in ascending order and then read and high byte should either
- * be zero or higher than the lower bytes.
- */
-
-static void init_test_data_u8(void)
-{
- uint8_t count = 0, *ptr = &test_data[0];
- int i;
-
- ml_printf("Filling test area with u8:");
- for (i = 0; i < TEST_SIZE; i++) {
- *ptr++ = count++;
- pdot(i);
- }
- ml_printf("done\n");
-}
-
-static void init_test_data_u16(int offset)
-{
- uint8_t count = 0;
- uint16_t word, *ptr = (uint16_t *) &test_data[0];
- const int max = (TEST_SIZE - offset) / sizeof(word);
- int i;
-
- ml_printf("Filling test area with u16 (offset %d):", offset);
-
- /* Leading zeros */
- for (i = 0; i < offset; i++) {
- *ptr = 0;
- }
-
- ptr = (uint16_t *) &test_data[offset];
- for (i = 0; i < max; i++) {
- uint8_t high, low;
- low = count++;
- high = count++;
- word = (high << 8) | low;
- *ptr++ = word;
- pdot(i);
- }
- ml_printf("done\n");
-}
-
-static void init_test_data_u32(int offset)
-{
- uint8_t count = 0;
- uint32_t word, *ptr = (uint32_t *) &test_data[0];
- const int max = (TEST_SIZE - offset) / sizeof(word);
- int i;
-
- ml_printf("Filling test area with u32 (offset %d):", offset);
-
- /* Leading zeros */
- for (i = 0; i < offset; i++) {
- *ptr = 0;
- }
-
- ptr = (uint32_t *) &test_data[offset];
- for (i = 0; i < max; i++) {
- uint8_t b1, b2, b3, b4;
- b4 = count++;
- b3 = count++;
- b2 = count++;
- b1 = count++;
- word = (b1 << 24) | (b2 << 16) | (b3 << 8) | b4;
- *ptr++ = word;
- pdot(i);
- }
- ml_printf("done\n");
-}
-
-
-static int read_test_data_u16(int offset)
-{
- uint16_t word, *ptr = (uint16_t *)&test_data[offset];
- int i;
- const int max = (TEST_SIZE - offset) / sizeof(word);
-
- ml_printf("Reading u16 from %#lx (offset %d):", ptr, offset);
-
- for (i = 0; i < max; i++) {
- uint8_t high, low;
- word = *ptr++;
- high = (word >> 8) & 0xff;
- low = word & 0xff;
- if (high < low && high != 0) {
- ml_printf("Error %d < %d\n", high, low);
- return 1;
- } else {
- pdot(i);
- }
-
- }
- ml_printf("done\n");
- return 0;
-}
-
-static int read_test_data_u32(int offset)
-{
- uint32_t word, *ptr = (uint32_t *)&test_data[offset];
- int i;
- const int max = (TEST_SIZE - offset) / sizeof(word);
-
- ml_printf("Reading u32 from %#lx (offset %d):", ptr, offset);
-
- for (i = 0; i < max; i++) {
- uint8_t b1, b2, b3, b4;
- word = *ptr++;
-
- b1 = word >> 24 & 0xff;
- b2 = word >> 16 & 0xff;
- b3 = word >> 8 & 0xff;
- b4 = word & 0xff;
-
- if ((b1 < b2 && b1 != 0) ||
- (b2 < b3 && b2 != 0) ||
- (b3 < b4 && b3 != 0)) {
- ml_printf("Error %d, %d, %d, %d", b1, b2, b3, b4);
- return 2;
- } else {
- pdot(i);
- }
- }
- ml_printf("done\n");
- return 0;
-}
-
-static int read_test_data_u64(int offset)
-{
- uint64_t word, *ptr = (uint64_t *)&test_data[offset];
- int i;
- const int max = (TEST_SIZE - offset) / sizeof(word);
-
- ml_printf("Reading u64 from %#lx (offset %d):", ptr, offset);
-
- for (i = 0; i < max; i++) {
- uint8_t b1, b2, b3, b4, b5, b6, b7, b8;
- word = *ptr++;
-
- b1 = ((uint64_t) (word >> 56)) & 0xff;
- b2 = ((uint64_t) (word >> 48)) & 0xff;
- b3 = ((uint64_t) (word >> 40)) & 0xff;
- b4 = (word >> 32) & 0xff;
- b5 = (word >> 24) & 0xff;
- b6 = (word >> 16) & 0xff;
- b7 = (word >> 8) & 0xff;
- b8 = (word >> 0) & 0xff;
-
- if ((b1 < b2 && b1 != 0) ||
- (b2 < b3 && b2 != 0) ||
- (b3 < b4 && b3 != 0) ||
- (b4 < b5 && b4 != 0) ||
- (b5 < b6 && b5 != 0) ||
- (b6 < b7 && b6 != 0) ||
- (b7 < b8 && b7 != 0)) {
- ml_printf("Error %d, %d, %d, %d, %d, %d, %d, %d",
- b1, b2, b3, b4, b5, b6, b7, b8);
- return 2;
- } else {
- pdot(i);
- }
- }
- ml_printf("done\n");
- return 0;
-}
-
-/* Read the test data and verify at various offsets */
-int do_reads(void)
-{
- int r = 0;
- int off = 0;
-
- while (r == 0 && off < 8) {
- r = read_test_data_u16(off);
- r |= read_test_data_u32(off);
- r |= read_test_data_u64(off);
- off++;
- }
-
- return r;
-}
-
-int main(void)
-{
- int i, r = 0;
-
-
- init_test_data_u8();
- r = do_reads();
- if (r) {
- return r;
- }
-
- for (i = 0; i < 8; i++) {
- init_test_data_u16(i);
-
- r = do_reads();
- if (r) {
- return r;
- }
- }
-
- for (i = 0; i < 8; i++) {
- init_test_data_u32(i);
-
- r = do_reads();
- if (r) {
- return r;
- }
- }
-
- ml_printf("Test complete: %s\n", r == 0 ? "PASSED" : "FAILED");
- return r;
-}
str = va_arg(ap, char*);
print_str(str);
break;
+ case 'c':
+ __sys_outc(va_arg(ap, int));
+ break;
case '%':
__sys_outc(*fmt);
break;
--- /dev/null
+# -*- Mode: makefile -*-
+#
+# Multiarch system tests
+#
+# We just collect the tests together here and rely on the actual guest
+# architecture to add to the test dependancies and deal with the
+# complications of building.
+#
+
+MULTIARCH_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/multiarch/system
+VPATH+=$(MULTIARCH_SYSTEM_SRC)
+
+MULTIARCH_TEST_SRCS=$(wildcard $(MULTIARCH_SYSTEM_SRC)/*.c)
+MULTIARCH_TESTS = $(patsubst $(MULTIARCH_SYSTEM_SRC)/%.c, %, $(MULTIARCH_TEST_SRCS))
--- /dev/null
+/*
+ * Memory Test
+ *
+ * This is intended to test the softmmu code and ensure we properly
+ * behave across normal and unaligned accesses across several pages.
+ * We are not replicating memory tests for stuck bits and other
+ * hardware level failures but looking for issues with different size
+ * accesses when access is:
+ *
+ * - unaligned at various sizes (if -DCHECK_UNALIGNED set)
+ * - spanning a (softmmu) page
+ * - sign extension when loading
+ */
+
+#include <inttypes.h>
+#include <stdbool.h>
+#include <minilib.h>
+
+#ifndef CHECK_UNALIGNED
+# error "Target does not specify CHECK_UNALIGNED"
+#endif
+
+#define PAGE_SIZE 4096 /* nominal 4k "pages" */
+#define TEST_SIZE (PAGE_SIZE * 4) /* 4 pages */
+
+#define ARRAY_SIZE(x) ((sizeof(x) / sizeof((x)[0])))
+
+__attribute__((aligned(PAGE_SIZE)))
+static uint8_t test_data[TEST_SIZE];
+
+typedef void (*init_ufn) (int offset);
+typedef bool (*read_ufn) (int offset);
+typedef bool (*read_sfn) (int offset, bool nf);
+
+static void pdot(int count)
+{
+ if (count % 128 == 0) {
+ ml_printf(".");
+ }
+}
+
+/*
+ * Helper macros for shift/extract so we can keep our endian handling
+ * in one place.
+ */
+#define BYTE_SHIFT(b, pos) ((uint64_t)b << (pos * 8))
+#define BYTE_EXTRACT(b, pos) ((b >> (pos * 8)) & 0xff)
+
+/*
+ * Fill the data with ascending value bytes.
+ *
+ * Currently we only support Little Endian machines so write in
+ * ascending address order. When we read higher address bytes should
+ * either be zero or higher than the lower bytes.
+ */
+
+static void init_test_data_u8(int unused_offset)
+{
+ uint8_t count = 0, *ptr = &test_data[0];
+ int i;
+ (void)(unused_offset);
+
+ ml_printf("Filling test area with u8:");
+ for (i = 0; i < TEST_SIZE; i++) {
+ *ptr++ = count++;
+ pdot(i);
+ }
+ ml_printf("done\n");
+}
+
+/*
+ * Full the data with alternating positive and negative bytes. This
+ * should mean for reads larger than a byte all subsequent reads will
+ * stay either negative or positive. We never write 0.
+ */
+
+static inline uint8_t get_byte(int index, bool neg)
+{
+ return neg ? (0xff << (index % 7)) : (0xff >> ((index % 6) + 1));
+}
+
+static void init_test_data_s8(bool neg_first)
+{
+ uint8_t top, bottom, *ptr = &test_data[0];
+ int i;
+
+ ml_printf("Filling test area with s8 pairs (%s):",
+ neg_first ? "neg first" : "pos first");
+ for (i = 0; i < TEST_SIZE / 2; i++) {
+ *ptr++ = get_byte(i, neg_first);
+ *ptr++ = get_byte(i, !neg_first);
+ pdot(i);
+ }
+ ml_printf("done\n");
+}
+
+/*
+ * Zero the first few bytes of the test data in preparation for
+ * new offset values.
+ */
+static void reset_start_data(int offset)
+{
+ uint32_t *ptr = (uint32_t *) &test_data[0];
+ int i;
+ for (i = 0; i < offset; i++) {
+ *ptr++ = 0;
+ }
+}
+
+static void init_test_data_u16(int offset)
+{
+ uint8_t count = 0;
+ uint16_t word, *ptr = (uint16_t *) &test_data[offset];
+ const int max = (TEST_SIZE - offset) / sizeof(word);
+ int i;
+
+ ml_printf("Filling test area with u16 (offset %d, %p):", offset, ptr);
+
+ reset_start_data(offset);
+
+ for (i = 0; i < max; i++) {
+ uint8_t low = count++, high = count++;
+ word = BYTE_SHIFT(high, 1) | BYTE_SHIFT(low, 0);
+ *ptr++ = word;
+ pdot(i);
+ }
+ ml_printf("done @ %p\n", ptr);
+}
+
+static void init_test_data_u32(int offset)
+{
+ uint8_t count = 0;
+ uint32_t word, *ptr = (uint32_t *) &test_data[offset];
+ const int max = (TEST_SIZE - offset) / sizeof(word);
+ int i;
+
+ ml_printf("Filling test area with u32 (offset %d, %p):", offset, ptr);
+
+ reset_start_data(offset);
+
+ for (i = 0; i < max; i++) {
+ uint8_t b4 = count++, b3 = count++;
+ uint8_t b2 = count++, b1 = count++;
+ word = BYTE_SHIFT(b1, 3) | BYTE_SHIFT(b2, 2) | BYTE_SHIFT(b3, 1) | b4;
+ *ptr++ = word;
+ pdot(i);
+ }
+ ml_printf("done @ %p\n", ptr);
+}
+
+static void init_test_data_u64(int offset)
+{
+ uint8_t count = 0;
+ uint64_t word, *ptr = (uint64_t *) &test_data[offset];
+ const int max = (TEST_SIZE - offset) / sizeof(word);
+ int i;
+
+ ml_printf("Filling test area with u64 (offset %d, %p):", offset, ptr);
+
+ reset_start_data(offset);
+
+ for (i = 0; i < max; i++) {
+ uint8_t b8 = count++, b7 = count++;
+ uint8_t b6 = count++, b5 = count++;
+ uint8_t b4 = count++, b3 = count++;
+ uint8_t b2 = count++, b1 = count++;
+ word = BYTE_SHIFT(b1, 7) | BYTE_SHIFT(b2, 6) | BYTE_SHIFT(b3, 5) |
+ BYTE_SHIFT(b4, 4) | BYTE_SHIFT(b5, 3) | BYTE_SHIFT(b6, 2) |
+ BYTE_SHIFT(b7, 1) | b8;
+ *ptr++ = word;
+ pdot(i);
+ }
+ ml_printf("done @ %p\n", ptr);
+}
+
+static bool read_test_data_u16(int offset)
+{
+ uint16_t word, *ptr = (uint16_t *)&test_data[offset];
+ int i;
+ const int max = (TEST_SIZE - offset) / sizeof(word);
+
+ ml_printf("Reading u16 from %#lx (offset %d):", ptr, offset);
+
+ for (i = 0; i < max; i++) {
+ uint8_t high, low;
+ word = *ptr++;
+ high = (word >> 8) & 0xff;
+ low = word & 0xff;
+ if (high < low && high != 0) {
+ ml_printf("Error %d < %d\n", high, low);
+ return false;
+ } else {
+ pdot(i);
+ }
+
+ }
+ ml_printf("done @ %p\n", ptr);
+ return true;
+}
+
+static bool read_test_data_u32(int offset)
+{
+ uint32_t word, *ptr = (uint32_t *)&test_data[offset];
+ int i;
+ const int max = (TEST_SIZE - offset) / sizeof(word);
+
+ ml_printf("Reading u32 from %#lx (offset %d):", ptr, offset);
+
+ for (i = 0; i < max; i++) {
+ uint8_t b1, b2, b3, b4;
+ word = *ptr++;
+
+ b1 = word >> 24 & 0xff;
+ b2 = word >> 16 & 0xff;
+ b3 = word >> 8 & 0xff;
+ b4 = word & 0xff;
+
+ if ((b1 < b2 && b1 != 0) ||
+ (b2 < b3 && b2 != 0) ||
+ (b3 < b4 && b3 != 0)) {
+ ml_printf("Error %d, %d, %d, %d", b1, b2, b3, b4);
+ return false;
+ } else {
+ pdot(i);
+ }
+ }
+ ml_printf("done @ %p\n", ptr);
+ return true;
+}
+
+static bool read_test_data_u64(int offset)
+{
+ uint64_t word, *ptr = (uint64_t *)&test_data[offset];
+ int i;
+ const int max = (TEST_SIZE - offset) / sizeof(word);
+
+ ml_printf("Reading u64 from %#lx (offset %d):", ptr, offset);
+
+ for (i = 0; i < max; i++) {
+ uint8_t b1, b2, b3, b4, b5, b6, b7, b8;
+ word = *ptr++;
+
+ b1 = ((uint64_t) (word >> 56)) & 0xff;
+ b2 = ((uint64_t) (word >> 48)) & 0xff;
+ b3 = ((uint64_t) (word >> 40)) & 0xff;
+ b4 = (word >> 32) & 0xff;
+ b5 = (word >> 24) & 0xff;
+ b6 = (word >> 16) & 0xff;
+ b7 = (word >> 8) & 0xff;
+ b8 = (word >> 0) & 0xff;
+
+ if ((b1 < b2 && b1 != 0) ||
+ (b2 < b3 && b2 != 0) ||
+ (b3 < b4 && b3 != 0) ||
+ (b4 < b5 && b4 != 0) ||
+ (b5 < b6 && b5 != 0) ||
+ (b6 < b7 && b6 != 0) ||
+ (b7 < b8 && b7 != 0)) {
+ ml_printf("Error %d, %d, %d, %d, %d, %d, %d, %d",
+ b1, b2, b3, b4, b5, b6, b7, b8);
+ return false;
+ } else {
+ pdot(i);
+ }
+ }
+ ml_printf("done @ %p\n", ptr);
+ return true;
+}
+
+/* Read the test data and verify at various offsets */
+read_ufn read_ufns[] = { read_test_data_u16,
+ read_test_data_u32,
+ read_test_data_u64 };
+
+bool do_unsigned_reads(void)
+{
+ int i;
+ bool ok = true;
+
+ for (i = 0; i < ARRAY_SIZE(read_ufns) && ok; i++) {
+#if CHECK_UNALIGNED
+ int off;
+ for (off = 0; off < 8 && ok; off++) {
+ ok = read_ufns[i](off);
+ }
+#else
+ ok = read_ufns[i](0);
+#endif
+ }
+
+ return ok;
+}
+
+static bool do_unsigned_test(init_ufn fn)
+{
+#if CHECK_UNALIGNED
+ bool ok = true;
+ int i;
+ for (i = 0; i < 8 && ok; i++) {
+ fn(i);
+ ok = do_unsigned_reads();
+ }
+#else
+ fn(0);
+ return do_unsigned_reads();
+#endif
+}
+
+/*
+ * We need to ensure signed data is read into a larger data type to
+ * ensure that sign extension is working properly.
+ */
+
+static bool read_test_data_s8(int offset, bool neg_first)
+{
+ int8_t *ptr = (int8_t *)&test_data[offset];
+ int i;
+ const int max = (TEST_SIZE - offset) / 2;
+
+ ml_printf("Reading s8 pairs from %#lx (offset %d):", ptr, offset);
+
+ for (i = 0; i < max; i++) {
+ int16_t first, second;
+ bool ok;
+ first = *ptr++;
+ second = *ptr++;
+
+ if (neg_first && first < 0 && second > 0) {
+ pdot(i);
+ } else if (!neg_first && first > 0 && second < 0) {
+ pdot(i);
+ } else {
+ ml_printf("Error %d %c %d\n", first, neg_first ? '<' : '>', second);
+ return false;
+ }
+ }
+ ml_printf("done @ %p\n", ptr);
+ return true;
+}
+
+static bool read_test_data_s16(int offset, bool neg_first)
+{
+ int16_t *ptr = (int16_t *)&test_data[offset];
+ int i;
+ const int max = (TEST_SIZE - offset) / (sizeof(*ptr));
+
+ ml_printf("Reading s16 from %#lx (offset %d, %s):", ptr,
+ offset, neg_first ? "neg" : "pos");
+
+ for (i = 0; i < max; i++) {
+ int32_t data = *ptr++;
+
+ if (neg_first && data < 0) {
+ pdot(i);
+ } else if (data > 0) {
+ pdot(i);
+ } else {
+ ml_printf("Error %d %c 0\n", data, neg_first ? '<' : '>');
+ return false;
+ }
+ }
+ ml_printf("done @ %p\n", ptr);
+ return true;
+}
+
+static bool read_test_data_s32(int offset, bool neg_first)
+{
+ int32_t *ptr = (int32_t *)&test_data[offset];
+ int i;
+ const int max = (TEST_SIZE - offset) / (sizeof(int32_t));
+
+ ml_printf("Reading s32 from %#lx (offset %d, %s):",
+ ptr, offset, neg_first ? "neg" : "pos");
+
+ for (i = 0; i < max; i++) {
+ int64_t data = *ptr++;
+
+ if (neg_first && data < 0) {
+ pdot(i);
+ } else if (data > 0) {
+ pdot(i);
+ } else {
+ ml_printf("Error %d %c 0\n", data, neg_first ? '<' : '>');
+ return false;
+ }
+ }
+ ml_printf("done @ %p\n", ptr);
+ return true;
+}
+
+/*
+ * Read the test data and verify at various offsets
+ *
+ * For everything except bytes all our reads should be either positive
+ * or negative depending on what offset we are reading from. Currently
+ * we only handle LE systems.
+ */
+read_sfn read_sfns[] = { read_test_data_s8,
+ read_test_data_s16,
+ read_test_data_s32 };
+
+bool do_signed_reads(bool neg_first)
+{
+ int i;
+ bool ok = true;
+
+ for (i = 0; i < ARRAY_SIZE(read_sfns) && ok; i++) {
+#if CHECK_UNALIGNED
+ int off;
+ for (off = 0; off < 8 && ok; off++) {
+ bool nf = i == 0 ? neg_first ^ (off & 1) : !(neg_first ^ (off & 1));
+ ok = read_sfns[i](off, nf);
+ }
+#else
+ ok = read_sfns[i](0, i == 0 ? neg_first : !neg_first);
+#endif
+ }
+
+ return ok;
+}
+
+init_ufn init_ufns[] = { init_test_data_u8,
+ init_test_data_u16,
+ init_test_data_u32,
+ init_test_data_u64 };
+
+int main(void)
+{
+ int i;
+ bool ok = true;
+
+ /* Run through the unsigned tests first */
+ for (i = 0; i < ARRAY_SIZE(init_ufns) && ok; i++) {
+ ok = do_unsigned_test(init_ufns[i]);
+ }
+
+ if (ok) {
+ init_test_data_s8(false);
+ ok = do_signed_reads(false);
+ }
+
+ if (ok) {
+ init_test_data_s8(true);
+ ok = do_signed_reads(true);
+ }
+
+ ml_printf("Test complete: %s\n", ok ? "PASSED" : "FAILED");
+ return ok ? 0 : -1;
+}
bdrv_unref(parent_b);
blk_unref(blk);
- /* XXX Once bdrv_close() unref's children instead of just detaching them,
- * this won't be necessary any more. */
- bdrv_unref(a);
- bdrv_unref(a);
- bdrv_unref(c);
-
g_assert_cmpint(a->refcnt, ==, 1);
g_assert_cmpint(b->refcnt, ==, 1);
g_assert_cmpint(c->refcnt, ==, 1);
g_assert_nonnull(local_err);
error_free(local_err);
- bdrv_unref(bs);
blk_unref(root);
}
#include "qapi/opts-visitor.h"
#include "qapi/clone-visitor.h"
#include "qom/object_interfaces.h"
-#include "exec/semihost.h"
+#include "hw/semihosting/semihost.h"
#include "crypto/init.h"
#include "sysemu/replay.h"
#include "qapi/qapi-events-run-state.h"
},
};
-static QemuOptsList qemu_semihosting_config_opts = {
- .name = "semihosting-config",
- .implied_opt_name = "enable",
- .head = QTAILQ_HEAD_INITIALIZER(qemu_semihosting_config_opts.head),
- .desc = {
- {
- .name = "enable",
- .type = QEMU_OPT_BOOL,
- }, {
- .name = "target",
- .type = QEMU_OPT_STRING,
- }, {
- .name = "arg",
- .type = QEMU_OPT_STRING,
- },
- { /* end of list */ }
- },
-};
-
static QemuOptsList qemu_fw_cfg_opts = {
.name = "fw_cfg",
.implied_opt_name = "name",
enable_timestamp_msg = qemu_opt_get_bool(opts, "timestamp", true);
}
-/***********************************************************/
-/* Semihosting */
-
-typedef struct SemihostingConfig {
- bool enabled;
- SemihostingTarget target;
- const char **argv;
- int argc;
- const char *cmdline; /* concatenated argv */
-} SemihostingConfig;
-
-static SemihostingConfig semihosting;
-
-bool semihosting_enabled(void)
-{
- return semihosting.enabled;
-}
-
-SemihostingTarget semihosting_get_target(void)
-{
- return semihosting.target;
-}
-
-const char *semihosting_get_arg(int i)
-{
- if (i >= semihosting.argc) {
- return NULL;
- }
- return semihosting.argv[i];
-}
-
-int semihosting_get_argc(void)
-{
- return semihosting.argc;
-}
-
-const char *semihosting_get_cmdline(void)
-{
- if (semihosting.cmdline == NULL && semihosting.argc > 0) {
- semihosting.cmdline = g_strjoinv(" ", (gchar **)semihosting.argv);
- }
- return semihosting.cmdline;
-}
-
-static int add_semihosting_arg(void *opaque,
- const char *name, const char *val,
- Error **errp)
-{
- SemihostingConfig *s = opaque;
- if (strcmp(name, "arg") == 0) {
- s->argc++;
- /* one extra element as g_strjoinv() expects NULL-terminated array */
- s->argv = g_realloc(s->argv, (s->argc + 1) * sizeof(void *));
- s->argv[s->argc - 1] = val;
- s->argv[s->argc] = NULL;
- }
- return 0;
-}
-
-/* Use strings passed via -kernel/-append to initialize semihosting.argv[] */
-static inline void semihosting_arg_fallback(const char *file, const char *cmd)
-{
- char *cmd_token;
-
- /* argv[0] */
- add_semihosting_arg(&semihosting, "arg", file, NULL);
-
- /* split -append and initialize argv[1..n] */
- cmd_token = strtok(g_strdup(cmd), " ");
- while (cmd_token) {
- add_semihosting_arg(&semihosting, "arg", cmd_token, NULL);
- cmd_token = strtok(NULL, " ");
- }
-}
/* Now we still need this for compatibility with XEN. */
bool has_igd_gfx_passthru;
nb_option_roms++;
break;
case QEMU_OPTION_semihosting:
- semihosting.enabled = true;
- semihosting.target = SEMIHOSTING_TARGET_AUTO;
+ qemu_semihosting_enable();
break;
case QEMU_OPTION_semihosting_config:
- semihosting.enabled = true;
- opts = qemu_opts_parse_noisily(qemu_find_opts("semihosting-config"),
- optarg, false);
- if (opts != NULL) {
- semihosting.enabled = qemu_opt_get_bool(opts, "enable",
- true);
- const char *target = qemu_opt_get(opts, "target");
- if (target != NULL) {
- if (strcmp("native", target) == 0) {
- semihosting.target = SEMIHOSTING_TARGET_NATIVE;
- } else if (strcmp("gdb", target) == 0) {
- semihosting.target = SEMIHOSTING_TARGET_GDB;
- } else if (strcmp("auto", target) == 0) {
- semihosting.target = SEMIHOSTING_TARGET_AUTO;
- } else {
- error_report("unsupported semihosting-config %s",
- optarg);
- exit(1);
- }
- } else {
- semihosting.target = SEMIHOSTING_TARGET_AUTO;
- }
- /* Set semihosting argument count and vector */
- qemu_opt_foreach(opts, add_semihosting_arg,
- &semihosting, NULL);
- } else {
- error_report("unsupported semihosting-config %s", optarg);
+ if (qemu_semihosting_config_options(optarg) != 0) {
exit(1);
}
break;
qemu_opts_foreach(qemu_find_opts("chardev"),
chardev_init_func, NULL, &error_fatal);
+ /* now chardevs have been created we may have semihosting to connect */
+ qemu_semihosting_connect_chardevs();
#ifdef CONFIG_VIRTFS
qemu_opts_foreach(qemu_find_opts("fsdev"),
projects / thirdparty / qemu.git / commitdiff
