x86/sev: Prevent SECURE_AVIC_CONTROL MSR interception for Secure AVIC guests

The SECURE_AVIC_CONTROL MSR holds the GPA of the guest APIC backing page and
bitfields to control enablement of Secure AVIC and whether the guest allows
NMIs to be injected by the hypervisor.

This MSR is populated by the guest and can be read by the guest to get the GPA
of the APIC backing page. The MSR can only be accessed in Secure AVIC mode.
Any attempt to access it when not in Secure AVIC mode results in #GP. So, the
hypervisor should not intercept it. A #VC exception will be generated
otherwise. If this occurs and Secure AVIC is enabled, terminate the guest
execution.

Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tianyu Lan <tiala@microsoft.com>
Link: https://lore.kernel.org/20250828113119.209135-1-Neeraj.Upadhyay@amd.com

diff --git a/arch/x86/coco/sev/vc-handle.c b/arch/x86/coco/sev/vc-handle.c
index c1aa10ce9d54432973fcc314125dde6d19ca6b03..0fd94b7ce19120ace681e263ba1ea3d8bb5b3e97 100644 (file)
--- a/arch/x86/coco/sev/vc-handle.c
+++ b/arch/x86/coco/sev/vc-handle.c
@@ -415,6 +415,15 @@ enum es_result sev_es_ghcb_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt
                if (sev_status & MSR_AMD64_SNP_SECURE_TSC)
                        return __vc_handle_secure_tsc_msrs(ctxt, write);
                break;
+       case MSR_AMD64_SAVIC_CONTROL:
+               /*
+                * AMD64_SAVIC_CONTROL should not be intercepted when
+                * Secure AVIC is enabled. Terminate the Secure AVIC guest
+                * if the interception is enabled.
+                */
+               if (cc_platform_has(CC_ATTR_SNP_SECURE_AVIC))
+                       return ES_VMM_ERROR;
+               break;
        default:
                break;
        }