drm/i915/cdclk: Extract vlv_dsi_min_cdclk()

Pull the DSI min cdclk calculation into a helper and hide
it inside vlv_dsi.c in order to keep most DSI related
details in one place.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241029215217.3697-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index fa887a5385385ad2a36741be47ab8090138e591d..34166d00766b7143b79894858a93b1d3a6d7aef7 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -46,6 +46,7 @@
 #include "intel_vdsc.h"
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
+#include "vlv_dsi.h"
 #include "vlv_sideband.h"
 
 /**
@@ -2849,8 +2850,6 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
 
 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
-       struct intel_display *display = to_intel_display(crtc_state);
-       struct drm_i915_private *dev_priv = to_i915(display->drm);
        int min_cdclk;
 
        if (!crtc_state->hw.enable)
@@ -2859,25 +2858,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
        min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
        min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
        min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
-
-       /*
-        * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
-        * than 320000KHz.
-        */
-       if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
-           IS_VALLEYVIEW(dev_priv))
-               min_cdclk = max(320000, min_cdclk);
-
-       /*
-        * On Geminilake once the CDCLK gets as low as 79200
-        * picture gets unstable, despite that values are
-        * correct for DSI PLL and DE PLL.
-        */
-       if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
-           IS_GEMINILAKE(dev_priv))
-               min_cdclk = max(158400, min_cdclk);
-
-       /* Account for additional needs from the planes */
+       min_cdclk = max(vlv_dsi_min_cdclk(crtc_state), min_cdclk);
        min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
 
        if (crtc_state->dsc.compression_enable)

diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 587e98d32053f133e577af745171f5c2c6f08c54..149cbfec5d48a03724f5e530d0143b17ac10b217 100644 (file)
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1759,6 +1759,31 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
        intel_dsi_log_params(intel_dsi);
 }
 
+int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+       struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+       int min_cdclk = 0;
+
+       /*
+        * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
+        * than 320000KHz.
+        */
+       if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
+           IS_VALLEYVIEW(dev_priv))
+               min_cdclk = max(320000, min_cdclk);
+
+       /*
+        * On Geminilake once the CDCLK gets as low as 79200
+        * picture gets unstable, despite that values are
+        * correct for DSI PLL and DE PLL.
+        */
+       if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
+           IS_GEMINILAKE(dev_priv))
+               min_cdclk = max(158400, min_cdclk);
+
+       return min_cdclk;
+}
+
 typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);
 
 /*

diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.h b/drivers/gpu/drm/i915/display/vlv_dsi.h
index a02fd7bd2f2a59522bff1f998bfe1f52316547d9..277bacfbc55129385584ccd3bd03b2655b539ea7 100644 (file)
--- a/drivers/gpu/drm/i915/display/vlv_dsi.h
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.h
@@ -8,15 +8,21 @@
 
 enum port;
 struct drm_i915_private;
+struct intel_crtc_state;
 struct intel_dsi;
 
 #ifdef I915
 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
+int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state);
 void vlv_dsi_init(struct drm_i915_private *dev_priv);
 #else
 static inline void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
 {
 }
+static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+       return 0;
+}
 static inline void vlv_dsi_init(struct drm_i915_private *dev_priv)
 {
 }