[RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask

A constraint here just makes it easier to understand what the
operands are.

OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with
--with-arch=rvNimafdc_zba_zbb_zbc_zbs (where N is 32 and 64).

Thanks,
Andrew Pinski

gcc/ChangeLog:

	* config/riscv/constraints.md (DsS): New constraint.
	(DsD): New constraint.
	* config/riscv/iterators.md (shiftm1c): New iterator.
	* config/riscv/bitmanip.md (*bset<mode>_mask):
	Use shiftm1c.
	(*bset<mode>_1_mask): Likewise.

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 258bd5a84fcdd62bb5d12397030a475660ebf629..73b2c1040b6eff26b5974ecaf6bbaa427d2e1f78 100644 (file)
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -297,7 +297,7 @@
        (ior:X (ashift:X (const_int 1)
                         (subreg:QI
                          (and:X (match_operand:X 2 "register_operand" "r")
-                                (match_operand 3 "<X:shiftm1>" "i")) 0))
+                                (match_operand 3 "<X:shiftm1>" "<X:shiftm1p>")) 0))
               (match_operand:X 1 "register_operand" "r")))]
   "TARGET_ZBS"
   "bset\t%0,%1,%2"
@@ -316,7 +316,7 @@
        (ashift:X (const_int 1)
                  (subreg:QI
                   (and:X (match_operand:X 1 "register_operand" "r")
-                         (match_operand 2 "<X:shiftm1>" "i")) 0)))]
+                         (match_operand 2 "<X:shiftm1>" "<X:shiftm1p>")) 0)))]
   "TARGET_ZBS"
   "bset\t%0,x0,%1"
   [(set_attr "type" "bitmanip")])

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 61b84875fd9e569c1343e11f90c1ca211a3b699f..444870ad060b4341e1f048dfe1c1c83eae6995d6 100644 (file)
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -60,6 +60,18 @@
   (and (match_code "const_int")
        (match_test "IN_RANGE (ival, 1, 3)")))
 
+(define_constraint "DsS"
+  "@internal
+   31 immediate"
+  (and (match_code "const_int")
+       (match_test "ival == 31")))
+
+(define_constraint "DsD"
+  "@internal
+   63 immediate"
+  (and (match_code "const_int")
+       (match_test "ival == 63")))
+
 ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
 ;; not available in RV32.
 (define_constraint "G"

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 2d7223d8a8a919f3b9b9056a861affbd2d921bb2..39dffabc235d428560d6d9ee0f426f7d89106abe 100644 (file)
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -114,6 +114,7 @@
 
 ; bitmanip mode attribute
 (define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
+(define_mode_attr shiftm1p [(SI "DsS") (DI "DsD")])
 
 ;; -------------------------------------------------------------------
 ;; Code Iterators