#define cfun_frame_layout (cfun->machine->frame_layout)
#define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
- cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
+ cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
#define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
(1 << (BITNUM)))
#define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
return TARGET_64BIT ? DImode : SImode;
}
+static enum machine_mode
+s390_unwind_word_mode (void)
+{
+ return TARGET_64BIT ? DImode : SImode;
+}
+
/* Return true if the back end supports mode MODE. */
static bool
s390_scalar_mode_supported_p (enum machine_mode mode)
{
+ /* In contrast to the default implementation reject TImode constants on 31bit
+ TARGET_ZARCH for ABI compliance. */
+ if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
+ return false;
+
if (DECIMAL_FLOAT_MODE_P (mode))
return default_decimal_float_supported_p ();
- else
- return default_scalar_mode_supported_p (mode);
+
+ return default_scalar_mode_supported_p (mode);
}
/* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
{
rtx left = XEXP (x, 0);
rtx right = XEXP (x, 1);
- if (TARGET_64BIT)
+ if (TARGET_ZARCH)
{
if (GET_CODE (right) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (right)))
{
rtx right = XEXP (x, 1);
if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
- if (TARGET_64BIT)
+ if (TARGET_ZARCH)
*total = s390_cost->dsgfr;
else
*total = s390_cost->dr;
if (MEM_P (x)
&& s390_symref_operand_p (XEXP (x, 0), NULL, NULL)
&& (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
- || (!TARGET_64BIT && mode == DImode)
+ || (!TARGET_ZARCH && mode == DImode)
|| ((mode == HImode || mode == SImode || mode == DImode)
&& (!s390_check_symref_alignment (XEXP (x, 0),
GET_MODE_SIZE (mode))))))
else
{
- rtx dst_addr, src_addr, count, blocks, temp, dstp1 = NULL_RTX;
+ rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
rtx loop_start_label = gen_label_rtx ();
rtx loop_end_label = gen_label_rtx ();
rtx end_label = gen_label_rtx ();
mode = Pmode;
dst_addr = gen_reg_rtx (Pmode);
- src_addr = gen_reg_rtx (Pmode);
count = gen_reg_rtx (mode);
blocks = gen_reg_rtx (mode);
return 4;
}
-
/* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
Fix up MEMs as required. */
}
if (TARGET_PACKED_STACK)
- offset = -2 * UNITS_PER_WORD;
+ offset = -2 * UNITS_PER_LONG;
else
- offset = RETURN_REGNUM * UNITS_PER_WORD;
+ offset = RETURN_REGNUM * UNITS_PER_LONG;
addr = plus_constant (frame, offset);
addr = memory_address (Pmode, addr);
if (TARGET_PACKED_STACK)
chain = plus_constant (stack_pointer_rtx,
- STACK_POINTER_OFFSET - UNITS_PER_WORD);
+ STACK_POINTER_OFFSET - UNITS_PER_LONG);
else
chain = stack_pointer_rtx;
if (cfun_frame_layout.first_restore_gpr != -1)
{
b = (cfun_frame_layout.gprs_offset
- + cfun_frame_layout.first_restore_gpr * UNITS_PER_WORD);
+ + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
t = b + (cfun_frame_layout.last_restore_gpr
- - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_WORD;
+ - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
}
if (TARGET_64BIT && cfun_save_high_fprs_p)
if (!TARGET_PACKED_STACK)
{
cfun_frame_layout.backchain_offset = 0;
- cfun_frame_layout.f0_offset = 16 * UNITS_PER_WORD;
+ cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
- * UNITS_PER_WORD);
+ * UNITS_PER_LONG);
}
else if (TARGET_BACKCHAIN) /* kernel stack layout */
{
cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
- - UNITS_PER_WORD);
+ - UNITS_PER_LONG);
cfun_frame_layout.gprs_offset
= (cfun_frame_layout.backchain_offset
- (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1)
- * UNITS_PER_WORD);
+ * UNITS_PER_LONG);
if (TARGET_64BIT)
{
else
{
if (TARGET_BACKCHAIN)
- cfun_frame_layout.frame_size += UNITS_PER_WORD;
+ cfun_frame_layout.frame_size += UNITS_PER_LONG;
/* No alignment trouble here because f8-f15 are only saved under
64 bit. */
case GENERAL_REGS:
if (REGNO_PAIR_OK (regno, mode))
{
- if (TARGET_64BIT
+ if (TARGET_ZARCH
|| (mode != TFmode && mode != TCmode && mode != TDmode))
return true;
}
index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot;
gcc_assert (index >= 0);
offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset;
- offset += index * UNITS_PER_WORD;
+ offset += index * UNITS_PER_LONG;
break;
case BASE_REGNUM:
if (start > last)
return insn;
- addr = plus_constant (base, offset + (start - first) * UNITS_PER_WORD);
+ addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG);
note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
gen_rtx_REG (Pmode, start),
GEN_INT (last - start + 1));
{
insn = save_gprs (stack_pointer_rtx,
cfun_frame_layout.gprs_offset +
- UNITS_PER_WORD * (cfun_frame_layout.first_save_gpr
+ UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
- cfun_frame_layout.first_save_gpr_slot),
cfun_frame_layout.first_save_gpr,
cfun_frame_layout.last_save_gpr);
addr = plus_constant (frame_pointer,
offset + cfun_frame_layout.gprs_offset
+ (i - cfun_frame_layout.first_save_gpr_slot)
- * UNITS_PER_WORD);
+ * UNITS_PER_LONG);
addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, get_frame_alias_set ());
emit_move_insn (addr, gen_rtx_REG (Pmode, i));
offset + cfun_frame_layout.gprs_offset
+ (RETURN_REGNUM
- cfun_frame_layout.first_save_gpr_slot)
- * UNITS_PER_WORD);
+ * UNITS_PER_LONG);
addr = gen_rtx_MEM (Pmode, addr);
set_mem_alias_set (addr, get_frame_alias_set ());
emit_move_insn (return_reg, addr);
offset + cfun_frame_layout.gprs_offset
+ (cfun_frame_layout.first_restore_gpr
- cfun_frame_layout.first_save_gpr_slot)
- * UNITS_PER_WORD,
+ * UNITS_PER_LONG,
cfun_frame_layout.first_restore_gpr,
cfun_frame_layout.last_restore_gpr);
insn = emit_insn (insn);
else if (s390_function_arg_integer (mode, type))
{
int size = s390_function_arg_size (mode, type);
- cum->gprs += ((size + UNITS_PER_WORD-1) / UNITS_PER_WORD);
+ cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
}
else
gcc_unreachable ();
else if (s390_function_arg_integer (mode, type))
{
int size = s390_function_arg_size (mode, type);
- int n_gprs = (size + UNITS_PER_WORD-1) / UNITS_PER_WORD;
+ int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
return 0;
- else
+ else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
return gen_rtx_REG (mode, cum->gprs + 2);
+ else if (n_gprs == 2)
+ {
+ rtvec p = rtvec_alloc (2);
+
+ RTVEC_ELT (p, 0)
+ = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
+ const0_rtx);
+ RTVEC_ELT (p, 1)
+ = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
+ GEN_INT (4));
+
+ return gen_rtx_PARALLEL (mode, p);
+ }
}
/* After the real arguments, expand_call calls us once again
int for_return ATTRIBUTE_UNUSED)
{
if (INTEGRAL_MODE_P (mode)
- && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
+ && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
{
if (POINTER_TYPE_P (type))
*punsignedp = POINTERS_EXTEND_UNSIGNED;
if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
return gen_rtx_REG (mode, 16);
- else
+ else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
+ || UNITS_PER_LONG == UNITS_PER_WORD)
return gen_rtx_REG (mode, 2);
+ else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
+ {
+ rtvec p = rtvec_alloc (2);
+
+ RTVEC_ELT (p, 0)
+ = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
+ RTVEC_ELT (p, 1)
+ = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
+
+ return gen_rtx_PARALLEL (mode, p);
+ }
+
+ gcc_unreachable ();
}
{
t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
- size_int (-RETURN_REGNUM * UNITS_PER_WORD));
+ size_int (-RETURN_REGNUM * UNITS_PER_LONG));
t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
TREE_SIDE_EFFECTS (t) = 1;
/* kernel stack layout on 31 bit: It is assumed here that no padding
will be added by s390_frame_info because for va_args always an even
number of gprs has to be saved r15-r2 = 14 regs. */
- sav_ofs = 2 * UNITS_PER_WORD;
- sav_scale = UNITS_PER_WORD;
- size = UNITS_PER_WORD;
+ sav_ofs = 2 * UNITS_PER_LONG;
+ sav_scale = UNITS_PER_LONG;
+ size = UNITS_PER_LONG;
max_reg = GP_ARG_NUM_REG - n_reg;
}
else if (s390_function_arg_float (TYPE_MODE (type), type))
indirect_p = 0;
reg = fpr;
n_reg = 1;
- sav_ofs = 16 * UNITS_PER_WORD;
+ sav_ofs = 16 * UNITS_PER_LONG;
sav_scale = 8;
max_reg = FP_ARG_NUM_REG - n_reg;
}
/* Otherwise into GP registers. */
indirect_p = 0;
reg = gpr;
- n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+ n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
/* kernel stack layout on 31 bit: It is assumed here that no padding
will be added by s390_frame_info because for va_args always an even
number of gprs has to be saved r15-r2 = 14 regs. */
- sav_ofs = 2 * UNITS_PER_WORD;
+ sav_ofs = 2 * UNITS_PER_LONG;
- if (size < UNITS_PER_WORD)
- sav_ofs += UNITS_PER_WORD - size;
+ if (size < UNITS_PER_LONG)
+ sav_ofs += UNITS_PER_LONG - size;
- sav_scale = UNITS_PER_WORD;
+ sav_scale = UNITS_PER_LONG;
max_reg = GP_ARG_NUM_REG - n_reg;
}
/* ... Otherwise out of the overflow area. */
t = ovf;
- if (size < UNITS_PER_WORD)
+ if (size < UNITS_PER_LONG)
t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
- size_int (UNITS_PER_WORD - size));
+ size_int (UNITS_PER_LONG - size));
gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
- op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_WORD));
+ op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG));
op[2] = gen_rtx_REG (Pmode, 1);
op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
s390_function_arg_advance (&cum, mode, type, 0);
- if (parm_rtx && REG_P (parm_rtx))
+ if (!parm_rtx)
+ continue;
+
+ if (REG_P (parm_rtx))
+ {
+ int n_regs;
+
+ /* Only integer registers (r6) are call saved and used for
+ parameter passing. */
+ if (REGNO_REG_CLASS (REGNO (parm_rtx)) == FP_REGS)
+ continue;
+
+ n_regs = ((GET_MODE_SIZE (GET_MODE (parm_rtx)) + UNITS_PER_LONG - 1)
+ / UNITS_PER_LONG);
+
+ for (reg = 0; reg < n_regs; reg++)
+ if (!call_used_regs[reg + REGNO (parm_rtx)])
+ return true;
+ }
+
+ if (GET_CODE (parm_rtx) == PARALLEL)
{
- for (reg = 0;
- reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
- reg++)
- if (! call_used_regs[reg + REGNO (parm_rtx)])
- return true;
+ int i;
+ for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
+ {
+ rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
+ int n_regs;
+
+ gcc_assert (REG_P (r));
+
+ /* Only integer registers (r6) are call saved and used
+ for parameter passing. */
+ if (REGNO_REG_CLASS (REGNO (r)) == FP_REGS)
+ continue;
+
+ n_regs = ((GET_MODE_SIZE (GET_MODE (r)) + UNITS_PER_LONG - 1)
+ / UNITS_PER_LONG);
+
+ for (reg = 0; reg < n_regs; reg++)
+ if (!call_used_regs[reg + REGNO (r)])
+ return true;
+ }
}
+
}
return false;
}
{
new_insn = save_gprs (base,
off + (cfun_frame_layout.first_save_gpr
- - first) * UNITS_PER_WORD,
+ - first) * UNITS_PER_LONG,
cfun_frame_layout.first_save_gpr,
cfun_frame_layout.last_save_gpr);
new_insn = emit_insn_before (new_insn, insn);
{
new_insn = restore_gprs (base,
off + (cfun_frame_layout.first_restore_gpr
- - first) * UNITS_PER_WORD,
+ - first) * UNITS_PER_LONG,
cfun_frame_layout.first_restore_gpr,
cfun_frame_layout.last_restore_gpr);
new_insn = emit_insn_before (new_insn, insn);
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
+
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION s390_handle_option
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
+#define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
+
#ifdef HAVE_AS_TLS
#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS true
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT s390_trampoline_init
+#undef TARGET_UNWIND_WORD_MODE
+#define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-s390.h"
;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
;; from the same template.
-(define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
+(define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
(define_mode_iterator DSI [DI SI])
;; These mode iterators allow :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
-(define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
+;; These macros refer to the actual word_mode of the configuration. This is equal
+;; to Pmode except on 31-bit machines in zarch mode.
+(define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
+(define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
+
;; This mode iterator allows the QI and HI patterns to be defined from
;; the same template.
(define_mode_iterator HQI [HI QI])
;; This mode iterator allows the integer patterns to be defined from the
;; same template.
-(define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
+(define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
(define_mode_iterator INTALL [TI DI SI HI QI])
;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
;; variant for long displacements.
(define_mode_attr y [(DI "g") (SI "y")])
-;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
+;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
;; and "cds" in DImode.
(define_mode_attr tg [(TI "g") (DI "")])
(match_operand:DI 1 "immediate_operand"
"N0HD0,N1HD0,N2HD0,N3HD0"))
(match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
- "TARGET_64BIT
+ "TARGET_ZARCH
&& s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
&& s390_single_part (operands[1], DImode, HImode, 0) >= 0"
"@
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d,d")
(sign_extend:DI (match_dup 0)))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
"ltgfr\t%2,%0
ltgf\t%2,%0"
[(set_attr "op_type" "RRE,RXY")
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d")
(match_dup 0))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
+ "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
"ltgr\t%2,%0"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_fr_E1")])
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
+ "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
"srda\t%0,0"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
(match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
- "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
"@
cgr\t%0,%1
cghi\t%0,%h1
(compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))]
- "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
"@
cgfr\t%0,%1
cgf\t%0,%1
(compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))]
- "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
"@
clgfr\t%0,%1
clgf\t%0,%1
"d, d,d,Q, d, Q,BQ")
(match_operand:DI 1 "general_operand"
"d,Op,b,D,RT,BQ,Q")))]
- "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
"@
clgr\t%0,%1
clgfi\t%0,%1
(define_insn "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
(match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
lmg\t%0,%N0,%S1
stmg\t%1,%N1,%S0
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], TImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], TImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:TI 0 "register_operand" "")
(match_operand:TI 1 "memory_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
{
rtx addr = operand_subword (operands[0], 1, 0, TImode);
+ addr = gen_lowpart (Pmode, addr);
s390_load_address (addr, XEXP (operands[1], 0));
operands[1] = replace_equiv_address (operands[1], addr);
})
(match_operand:DI 1 "general_operand"
"K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
lghi\t%0,%h1
llihh\t%0,%i1
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
- "TARGET_64BIT && ACCESS_REG_P (operands[1])"
+ "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
(set (strict_low_part (match_dup 2)) (match_dup 4))]
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
- "TARGET_64BIT && ACCESS_REG_P (operands[0])
+ "TARGET_ZARCH && ACCESS_REG_P (operands[0])
&& dead_or_set_p (insn, operands[1])"
[(set (match_dup 3) (match_dup 2))
(set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
- "TARGET_64BIT && ACCESS_REG_P (operands[0])
+ "TARGET_ZARCH && ACCESS_REG_P (operands[0])
&& !dead_or_set_p (insn, operands[1])"
[(set (match_dup 3) (match_dup 2))
(set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
"=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
(match_operand:DI 1 "general_operand"
" Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
lm\t%0,%N0,%S1
lmy\t%0,%N0,%S1
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))]
- "!TARGET_64BIT && reload_completed && TARGET_Z10
+ "!TARGET_ZARCH && reload_completed && TARGET_Z10
&& larl_operand (XEXP (operands[1], 0), SImode)"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 0) (match_dup 1))]
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], DImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], DImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(mem:DI (match_operand 1 "address_operand" "")))]
- "TARGET_64BIT
+ "TARGET_ZARCH
&& !FP_REG_P (operands[0])
&& GET_CODE (operands[1]) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (operands[1])
&& register_operand (operands[0], VOIDmode)
&& GET_CODE (operands[1]) == MEM)
{
- rtx tmp = gen_reg_rtx (word_mode);
- rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
+ rtx tmp = gen_reg_rtx (DImode);
+ rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
operands[1] = gen_lowpart (QImode, tmp);
}
(define_insn "movstrictsi"
[(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
(match_operand:SI 1 "general_operand" "d,R,T,t"))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
lr\t%0,%1
l\t%0,%1
(define_insn "*mov<mode>_64"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
lzxr\t%0
lxr\t%0,%1
(define_insn "*mov<mode>_31"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
lzxr\t%0
lxr\t%0,%1
(define_split
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:TD_TF 0 "register_operand" "")
(match_operand:TD_TF 1 "memory_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
"=f,f,f,d,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand"
" G,f,d,f,R,T,f,f,d,RT, d"))]
- "TARGET_64BIT && TARGET_DFP"
+ "TARGET_DFP"
"@
lzdr\t%0
ldr\t%0,%1
(define_insn "*mov<mode>_64"
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
(match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
lzdr\t%0
ldr\t%0,%1
"=f,f,f,f,R,T,d,d,Q,S, d,o")
(match_operand:DD_DF 1 "general_operand"
" G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
lzdr\t%0
ldr\t%0,%1
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:DD_DF 0 "register_operand" "")
(match_operand:DD_DF 1 "memory_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
count = INTVAL (operands[2]);
regno = REGNO (operands[0]);
mode = GET_MODE (operands[0]);
- if (mode != SImode && mode != word_mode)
+ if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
(match_operand:DI 2 "s_operand" "QS"))])]
- "reload_completed && word_mode == DImode"
+ "reload_completed && TARGET_ZARCH"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
count = INTVAL (operands[2]);
regno = REGNO (operands[1]);
mode = GET_MODE (operands[1]);
- if (mode != SImode && mode != word_mode)
+ if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:DI 1 "s_operand" "=QS")
(match_operand:DI 2 "register_operand" "r"))])]
- "reload_completed && word_mode == DImode"
+ "reload_completed && TARGET_ZARCH"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
(clobber (reg:CC CC_REGNUM))])]
""
{
- enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
- rtx reg0 = gen_reg_rtx (dword_mode);
- rtx reg1 = gen_reg_rtx (dword_mode);
- rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
- rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
+ enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
+ enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
+ rtx reg0 = gen_reg_rtx (dreg_mode);
+ rtx reg1 = gen_reg_rtx (dreg_mode);
+ rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
+ rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1);
(use (match_dup 2))
(use (match_dup 3))
(clobber (reg:CC CC_REGNUM))]
- ""
+ "TARGET_64BIT || !TARGET_ZARCH"
+ "mvcle\t%0,%1,0\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
+
+(define_insn "*movmem_long_31z"
+ [(clobber (match_operand:TI 0 "register_operand" "=d"))
+ (clobber (match_operand:TI 1 "register_operand" "=d"))
+ (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
+ (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
+ (use (match_dup 2))
+ (use (match_dup 3))
+ (clobber (reg:CC CC_REGNUM))]
+ "!TARGET_64BIT && TARGET_ZARCH"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
(clobber (reg:CC CC_REGNUM))])]
""
{
- enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
- rtx reg0 = gen_reg_rtx (dword_mode);
- rtx reg1 = gen_reg_rtx (dword_mode);
- rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
+ enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
+ enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
+ rtx reg0 = gen_reg_rtx (dreg_mode);
+ rtx reg1 = gen_reg_rtx (dreg_mode);
+ rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
rtx len0 = gen_lowpart (Pmode, reg0);
emit_clobber (reg0);
(use (match_dup 3))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
- ""
+ "TARGET_64BIT || !TARGET_ZARCH"
"mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
(use (match_dup 3))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
- "(INTVAL (operands[4]) & 255) == 255"
+ "(TARGET_64BIT || !TARGET_ZARCH) &&
+ (INTVAL (operands[4]) & 255) == 255"
+ "mvcle\t%0,%1,%Y2\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
+
+(define_insn "*setmem_long_31z"
+ [(clobber (match_operand:TI 0 "register_operand" "=d"))
+ (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
+ (match_operand 2 "shift_count_or_setmem_operand" "Y"))
+ (use (match_dup 3))
+ (use (match_operand:TI 1 "register_operand" "d"))
+ (clobber (reg:CC CC_REGNUM))]
+ "!TARGET_64BIT && TARGET_ZARCH"
"mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
+
;
; cmpmemM instruction pattern(s).
;
(use (match_dup 3))])]
""
{
- enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
- rtx reg0 = gen_reg_rtx (dword_mode);
- rtx reg1 = gen_reg_rtx (dword_mode);
- rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
- rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
+ enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
+ enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
+ rtx reg0 = gen_reg_rtx (dreg_mode);
+ rtx reg1 = gen_reg_rtx (dreg_mode);
+ rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
+ rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1);
(mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
(use (match_dup 2))
(use (match_dup 3))]
- ""
+ "TARGET_64BIT || !TARGET_ZARCH"
"clcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
+(define_insn "*cmpmem_long_31z"
+ [(clobber (match_operand:TI 0 "register_operand" "=d"))
+ (clobber (match_operand:TI 1 "register_operand" "=d"))
+ (set (reg:CCU CC_REGNUM)
+ (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
+ (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
+ (use (match_dup 2))
+ (use (match_dup 3))]
+ "!TARGET_64BIT && TARGET_ZARCH"
+ "clcle\t%0,%1,0\;jo\t.-4"
+ [(set_attr "op_type" "NN")
+ (set_attr "type" "vs")
+ (set_attr "length" "8")])
+
; Convert CCUmode condition code to integer.
; Result is zero if EQ, positive if LTU, negative if GTU.
(sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
UNSPEC_CCU_TO_INT)))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
(unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
(match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"icmh\t%0,%2,%S1"
[(set_attr "op_type" "RSY")
(set_attr "z10prop" "z10_super")])
(unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
(match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
icm\t%0,%2,%S1
icmy\t%0,%2,%S1"
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
- [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
+ [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
(match_operand 1 "const_int_operand" "n,n")
(const_int 0))
- (match_operand:P 2 "register_operand" "d,d"))]
+ (match_operand:W 2 "register_operand" "d,d"))]
"INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
(const_int 0))
(lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
(const_int 32)))]
- "TARGET_64BIT
+ "TARGET_ZARCH
&& INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
[(set_attr "op_type" "RSY")
(set_attr "z10prop" "z10_super")])
-(define_insn "*insv<mode>_reg_imm"
- [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
- (const_int 16)
- (match_operand 1 "const_int_operand" "n"))
- (match_operand:P 2 "const_int_operand" "n"))]
+(define_insn "*insvdi_reg_imm"
+ [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+ (const_int 16)
+ (match_operand 1 "const_int_operand" "n"))
+ (match_operand:DI 2 "const_int_operand" "n"))]
"TARGET_ZARCH
&& INTVAL (operands[1]) >= 0
&& INTVAL (operands[1]) < BITS_PER_WORD
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
{
- if (!TARGET_64BIT)
+ if (!TARGET_ZARCH)
{
emit_clobber (operands[0]);
emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
(define_insn "*extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
lgfr\t%0,%1
lgf\t%0,%1
(sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
{
- if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
+ if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
(define_insn "*extendhidi2_extimm"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
- "TARGET_64BIT && TARGET_EXTIMM"
+ "TARGET_ZARCH && TARGET_EXTIMM"
"@
lghr\t%0,%1
lgh\t%0,%1
(define_insn "*extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"lgh\t%0,%1"
[(set_attr "op_type" "RXY")
(set_attr "z10prop" "z10_super_E1")])
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
{
- if (!TARGET_64BIT)
+ if (!TARGET_ZARCH)
{
emit_clobber (operands[0]);
emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
(define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
llgfr\t%0,%1
llgf\t%0,%1
[(set (match_operand:DI 0 "register_operand" "=d")
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647)))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"llgt\t%0,%1"
[(set_attr "op_type" "RXE")
(set_attr "z10prop" "z10_super_E1")])
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0)
[(set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
(const_int 2147483647)))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
llgtr\t%0,%1
llgt\t%0,%N1"
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_split
- [(set (match_operand:GPR 0 "register_operand" "")
- (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
+ [(set (match_operand:DSI 0 "register_operand" "")
+ (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && reload_completed"
[(set (match_dup 0)
- (and:GPR (match_dup 1)
+ (and:DSI (match_dup 1)
(const_int 2147483647)))]
"")
(zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
{
- if (!TARGET_64BIT)
+ if (!TARGET_ZARCH)
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
(define_expand "fix_trunc<mode>di2"
[(set (match_operand:DI 0 "register_operand" "")
(fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_DFP"
+ "TARGET_ZARCH && TARGET_HARD_DFP"
{
operands[1] = force_reg (<MODE>mode, operands[1]);
emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
(fix:DI (match_operand:DFP 1 "register_operand" "f")))
(unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && TARGET_HARD_DFP"
+ "TARGET_ZARCH && TARGET_HARD_DFP"
"cg<DFP:xde>tr\t%0,%h2,%1"
[(set_attr "op_type" "RRF")
(set_attr "type" "ftoidfp")])
(define_insn "floatdi<mode>2"
[(set (match_operand:FP 0 "register_operand" "=f")
(float:FP (match_operand:DI 1 "register_operand" "d")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT"
+ "TARGET_ZARCH && TARGET_HARD_FLOAT"
"c<xde>g<bt>r\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof<mode>" )])
(plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
(match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
(plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
agfr\t%0,%2
agf\t%0,%2"
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
algfr\t%0,%2
algf\t%0,%2"
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
algfr\t%0,%2
algf\t%0,%2"
(plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
algfr\t%0,%2
algf\t%0,%2"
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
(minus:TI (match_operand:TI 1 "register_operand" "0")
(match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
sgfr\t%0,%2
sgf\t%0,%2"
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
slgfr\t%0,%2
slgf\t%0,%2"
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
slgfr\t%0,%2
slgf\t%0,%2"
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
slgfr\t%0,%2
slgf\t%0,%2"
(minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
[(set (match_operand:DI 0 "register_operand" "=d,d")
(mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
msgfr\t%0,%2
msgf\t%0,%2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
msgr\t%0,%2
mghi\t%0,%h2
(match_operand:SI 1 "register_operand" "%0,0,0"))
(sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
mr\t%0,%2
m\t%0,%2
(match_operand:SI 1 "register_operand" "%0,0"))
(zero_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"@
mlr\t%0,%2
ml\t%0,%2"
(set (match_operand:DI 3 "general_operand" "")
(mod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
{
rtx insn, div_equal, mod_equal;
(match_operand:DI 2 "general_operand" "d,RT")))
(const_int 64))
(zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
dsgr\t%0,%2
dsg\t%0,%2"
(const_int 64))
(zero_extend:TI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
dsgfr\t%0,%2
dsgf\t%0,%2"
(set (match_operand:DI 3 "general_operand" "")
(umod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
{
rtx insn, div_equal, mod_equal, equal;
(zero_extend:TI
(truncate:DI
(udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
dlgr\t%0,%2
dlg\t%0,%2"
(set (match_operand:SI 3 "general_operand" "")
(mod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
{
rtx insn, div_equal, mod_equal, equal;
(zero_extend:DI
(truncate:SI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
dr\t%0,%2
d\t%0,%2"
(set (match_operand:SI 3 "general_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
{
rtx insn, div_equal, mod_equal, equal;
(zero_extend:DI
(truncate:SI
(udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"@
dlr\t%0,%2
dl\t%0,%2"
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))
(clobber (match_dup 3))]
- "!TARGET_64BIT && !TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
{
rtx insn, udiv_equal, umod_equal, equal;
(umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "nonimmediate_operand" "")))
(clobber (match_dup 3))]
- "!TARGET_64BIT && !TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
{
rtx insn, udiv_equal, umod_equal, equal;
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
ngr\t%0,%2
ng\t%0,%2"
(match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@
(match_operand:DI 2 "general_operand"
"M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
+ "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
#
#
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(ior:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
ogr\t%0,%2
og\t%0,%2"
(match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
ogr\t%0,%2
og\t%0,%2"
(match_operand:DI 2 "general_operand"
"N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
+ "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
oihh\t%0,%i2
oihl\t%0,%i2
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(xor:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
xgr\t%0,%2
xg\t%0,%2"
(match_operand:DI 2 "general_operand" "d,RT"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
xgr\t%0,%2
xg\t%0,%2"
(xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
(match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
+ "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
xihf\t%0,%k2
xilf\t%0,%k2
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_dup 1))))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
+ "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_dup 1))))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
+ "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
[(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
+ "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lngfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
(neg:DI (abs:DI (sign_extend:DI
(match_operand:SI 1 "register_operand" "d")))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"lngfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
(define_expand "clzdi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(clz:DI (match_operand:DI 1 "register_operand" "d")))]
- "TARGET_EXTIMM && TARGET_64BIT"
+ "TARGET_EXTIMM && TARGET_ZARCH"
{
rtx insn, clz_equal;
rtx wide_reg = gen_reg_rtx (TImode);
(clobber (reg:CC CC_REGNUM))]
"(unsigned HOST_WIDE_INT) INTVAL (operands[2])
== (unsigned HOST_WIDE_INT) 1 << 63
- && TARGET_EXTIMM && TARGET_64BIT"
+ && TARGET_EXTIMM && TARGET_ZARCH"
"flogr\t%0,%1"
[(set_attr "op_type" "RRE")])
[(set (match_operand:DI 0 "register_operand" "=d")
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
(match_operand:SI 3 "const_int_operand" "n"))))]
- "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
+ "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
"s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
- "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
+ "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
- "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
+ "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
- "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
+ "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
&& (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(match_operand:SI 3 "const_int_operand" "n")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
- "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
+ "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
&& (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
(match_operand:SI 3 "const_int_operand" "n"))))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
+ "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(subreg:DI (match_dup 2) 0)))
(clobber (match_scratch:DI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
{
if (which_alternative != 0)
return "#";
(subreg:SI (match_dup 2) 4)))
(clobber (match_scratch:SI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
{
if (which_alternative != 0)
return "#";
(subreg:SI (match_dup 2) 0)))
(clobber (match_scratch:SI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
{
if (which_alternative != 0)
return "#";
emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
- else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
+ else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
else
FAIL;
(plus:DI (match_dup 1) (const_int -1)))
(clobber (match_scratch:DI 3 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
{
if (which_alternative != 0)
return "#";
; cds, cdsg
(define_insn "*sync_compare_and_swap<mode>"
- [(set (match_operand:DP 0 "register_operand" "=r")
- (match_operand:DP 1 "memory_operand" "+Q"))
+ [(set (match_operand:DW 0 "register_operand" "=r")
+ (match_operand:DW 1 "memory_operand" "+Q"))
(set (match_dup 1)
- (unspec_volatile:DP
+ (unspec_volatile:DW
[(match_dup 1)
- (match_operand:DP 2 "register_operand" "0")
- (match_operand:DP 3 "register_operand" "r")]
+ (match_operand:DW 2 "register_operand" "0")
+ (match_operand:DW 3 "register_operand" "r")]
UNSPECV_CAS))
(set (reg:CCZ1 CC_REGNUM)
(compare:CCZ1 (match_dup 1) (match_dup 2)))]
(match_operand 1 "register_operand" "")]
""
{
- enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
/* Copy the backchain to the first word, sp to the second and the
literal pool base to the third. */
+ rtx save_bc = adjust_address (operands[0], Pmode, 0);
+ rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
+ rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
+
if (TARGET_BACKCHAIN)
- {
- rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
- emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
- }
+ emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
- emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
- emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
+ emit_move_insn (save_sp, operands[1]);
+ emit_move_insn (save_bp, base);
DONE;
})
(match_operand 1 "memory_operand" "")]
""
{
- enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
rtx temp = NULL_RTX;
/* Restore the backchain from the first word, sp from the second and the
literal pool base from the third. */
+ rtx save_bc = adjust_address (operands[1], Pmode, 0);
+ rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
+ rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
+
if (TARGET_BACKCHAIN)
- temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
+ temp = force_reg (Pmode, save_bc);
- emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
- emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
+ emit_move_insn (base, save_bp);
+ emit_move_insn (operands[0], save_sp);
if (temp)
emit_move_insn (s390_back_chain_rtx (), temp);