#define PCI_EXT_CAP_ID_ALT_PROT 0x2b /* Alternate Protocol */
#define PCI_EXT_CAP_ID_SFI 0x2c /* System Firmware Intermediary */
#define PCI_EXT_CAP_ID_DOE 0x2e /* Data Object Exchange */
+#define PCI_EXT_CAP_ID_DEV3 0x2f /* Device 3 */
#define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */
#define PCI_EXT_CAP_ID_64GT 0x31 /* Physical Layer 64.0 GT/s */
#define PCI_EXT_CAP_ID_FLIT_LOG 0x32 /* Flit Logging */
#define PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
+#define PCI_EXP_FLAGS_FLIT_MODE 0x8000 /* FLIT mode supported */
#define PCI_EXP_DEVCAP 0x4 /* Device capabilities */
#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
#define PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
#define PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
#define PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
+#define PCI_EXP_LNKCTL_FLIT_MODE_DIS 0x2000 /* FLIT mode disable */
#define PCI_EXP_LNKSTA 0x12 /* Link Status */
#define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
#define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
#define PCI_EXP_LINKSTA2_CROSSLINK(x) (((x) >> 8) & 0x3) /* Crosslink Res */
#define PCI_EXP_LINKSTA2_COMPONENT(x) (((x) >> 12) & 0x7) /* Presence */
#define PCI_EXP_LINKSTA2_DRS_RCVD 0x8000 /* DRS Msg Received */
+#define PCI_EXP_LINKSTA2_FLIT_MODE 0x0400 /* FLIT mode active */
#define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */
#define PCI_EXP_SLTCTL2 0x38 /* Slot Control */
#define PCI_EXP_SLTSTA2 0x3a /* Slot Status */
#define PCI_LMR_PORT_STS_READY 0x1 /* Margining Ready */
#define PCI_LMR_PORT_STS_SOFT_READY 0x2 /* Margining Software Ready */
+/* Device 3 Extended Capability */
+#define PCI_DEV3_DEVCAP3 0x04 /* Device Capabilities 3 */
+#define PCI_DEV3_DEVCAP3_DMWR_REQ 0x0001 /* DMWr Request Routing Supported */
+#define PCI_DEV3_DEVCAP3_14BIT_TAG_COMP 0x0002 /* 14-Bit Tag Completer Supported */
+#define PCI_DEV3_DEVCAP3_14BIT_TAG_REQ 0x0004 /* 14-Bit Tag Requester Supported */
+#define PCI_DEV3_DEVCAP3_L0P_SUPP 0x0008 /* L0p Supported */
+#define PCI_DEV3_DEVCAP3_PORT_L0P_EXIT(x) (((x) >> 4) & 0x7) /* Port L0p Exit Latency */
+#define PCI_DEV3_DEVCAP3_RETIMER_L0P_EXIT(x) (((x) >> 7) & 0x7) /* Retimer L0p Exit Latency */
+#define PCI_DEV3_DEVCAP3_UIO_MEM_RDWR_COMP 0x0400 /* UIO Mem RdWr Completer Supported */
+#define PCI_DEV3_DEVCAP3_UIO_MEM_RDWR_REQ 0x0800 /* UIO Mem RdWr Requester Supported */
+
+#define PCI_DEV3_DEVCTL3 0x08 /* Device Control 3 */
+#define PCI_DEV3_DEVCTL3_DMWR_REQ_EN 0x0001 /* DMWr Requester Enable */
+#define PCI_DEV3_DEVCTL3_DMWR_EGRESS_BLK 0x0002 /* DMWr Egress Blocking */
+#define PCI_DEV3_DEVCTL3_14BIT_TAG_REQ_EN 0x0004 /* 14-Bit Tag Requester Enable */
+#define PCI_DEV3_DEVCTL3_L0P_EN 0x0008 /* L0p Enable */
+#define PCI_DEV3_DEVCTL3_TARGET_LINK_WIDTH(x) (((x) >> 4) & 0x7) /* Target Link Width */
+#define PCI_DEV3_DEVCTL3_UIO_MEM_RDWR_REQ_EN 0x0080 /* UIO Mem RdWr Requester Enable */
+#define PCI_DEV3_DEVCTL3_UIO_REQ_256B_DIS 0x0100 /* UIO Request 256B Boundary Disable */
+
+#define PCI_DEV3_DEVSTA3 0x0C /* Device Status 3 */
+#define PCI_DEV3_DEVSTA3_INIT_LINK_WIDTH(x) ((x) & 0x7) /* Initial Link Width */
+#define PCI_DEV3_DEVSTA3_SEGMENT_CAPTURED 0x0008 /* Segment Captured */
+#define PCI_DEV3_DEVSTA3_REMOTE_L0P_SUPP 0x0010 /* Remote L0p Supported */
+
/* Integrity and Data Encryption Extended Capability */
#define PCI_IDE_CAP 0x4
#define PCI_IDE_CAP_LINK_IDE_SUPP 0x1 /* Link IDE Stream Supported */
if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
(type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
- printf(" LnkDisable%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
+ printf(" LnkDisable%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c FltModeDis%c\n",
FLAG(w, PCI_EXP_LNKCTL_DISABLE),
FLAG(w, PCI_EXP_LNKCTL_CLOCK),
FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
FLAG(w, PCI_EXP_LNKCTL_BWMIE),
- FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
+ FLAG(w, PCI_EXP_LNKCTL_AUTBWIE),
+ FLAG(w, PCI_EXP_LNKCTL_FLIT_MODE_DIS));
w = get_conf_word(d, where + PCI_EXP_LNKSTA);
sta_speed = w & PCI_EXP_LNKSTA_SPEED;
w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n"
"\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n"
- "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s",
+ "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s, FltMode%c",
cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ),
FLAG(w, PCI_EXP_LINKSTA2_RETIMER),
FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS),
- cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w)));
+ cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w)),
+ FLAG(w, PCI_EXP_LINKSTA2_FLIT_MODE));
if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) {
printf(", DRS%c\n"
default:
printf("Unknown type %d", type);
}
- printf(", IntMsgNum %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
+ printf(", IntMsgNum %d", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
+ if (cap & PCI_EXP_FLAGS_FLIT_MODE)
+ printf(", FLIT Mode Supported\n");
+ else
+ printf("\n");
+
if (verbose < 2)
return type;
}
}
+static const char *l0p_exit_latency(int value)
+{
+ static const char *latencies[] = {
+ "Less than 1us",
+ "1us to less than 2us",
+ "2us to less than 4us",
+ "4us to less than 8us",
+ "8us to less than 16us",
+ "16us to less than 32us",
+ "32us-64us",
+ "More than 64us"
+ };
+
+ if (value >= 0 && value <= 7)
+ return latencies[value];
+ return "Unknown";
+}
+
+static const char *link_width_str(char *buf, size_t buflen, int width)
+{
+ switch (width)
+ {
+ case 0:
+ return "x1";
+ case 1:
+ return "x2";
+ case 2:
+ return "x4";
+ case 3:
+ return "x8";
+ case 4:
+ return "x16";
+ case 7:
+ return "Dynamic";
+ default:
+ snprintf(buf, buflen, "Unknown (%d)", width);
+ return buf;
+ }
+}
+
+static void
+cap_dev3(struct device *d, int where)
+{
+ u32 devcap3;
+ u16 devctl3, devsta3;
+ char buf[16];
+
+ printf("Device 3\n");
+
+ if (verbose < 2)
+ return;
+
+ if (!config_fetch(d, where + PCI_DEV3_DEVCAP3, 4))
+ return;
+ devcap3 = get_conf_long(d, where + PCI_DEV3_DEVCAP3);
+
+ printf("\t\tDevCap3: DMWr Request Routing%c, 14-Bit Tag Completer%c, 14-Bit Tag Requester%c\n"
+ "\t\t\t L0p%c",
+ FLAG(devcap3, PCI_DEV3_DEVCAP3_DMWR_REQ),
+ FLAG(devcap3, PCI_DEV3_DEVCAP3_14BIT_TAG_COMP),
+ FLAG(devcap3, PCI_DEV3_DEVCAP3_14BIT_TAG_REQ),
+ FLAG(devcap3, PCI_DEV3_DEVCAP3_L0P_SUPP));
+
+ if (devcap3 & PCI_DEV3_DEVCAP3_L0P_SUPP)
+ printf(", Port L0p Exit Latency: %s, Retimer L0p Exit Latency: %s",
+ l0p_exit_latency(PCI_DEV3_DEVCAP3_PORT_L0P_EXIT(devcap3)),
+ l0p_exit_latency(PCI_DEV3_DEVCAP3_RETIMER_L0P_EXIT(devcap3)));
+
+ printf("\n\t\t\t UIO Mem RdWr Completer%c, UIO Mem RdWr Requester%c\n",
+ FLAG(devcap3, PCI_DEV3_DEVCAP3_UIO_MEM_RDWR_COMP),
+ FLAG(devcap3, PCI_DEV3_DEVCAP3_UIO_MEM_RDWR_REQ));
+
+ if (!config_fetch(d, where + PCI_DEV3_DEVCTL3, 2))
+ return;
+ devctl3 = get_conf_word(d, where + PCI_DEV3_DEVCTL3);
+
+ printf("\t\tDevCtl3: DMWr Requester%c, DMWr Egress Blocking%c, 14-Bit Tag Requester%c\n"
+ "\t\t\t L0p%c, Target Link Width: %s\n"
+ "\t\t\t UIO Mem RdWr Requester%c, UIO Request 256B Boundary%c\n",
+ FLAG(devctl3, PCI_DEV3_DEVCTL3_DMWR_REQ_EN),
+ FLAG(devctl3, PCI_DEV3_DEVCTL3_DMWR_EGRESS_BLK),
+ FLAG(devctl3, PCI_DEV3_DEVCTL3_14BIT_TAG_REQ_EN),
+ FLAG(devctl3, PCI_DEV3_DEVCTL3_L0P_EN),
+ link_width_str(buf, sizeof(buf), PCI_DEV3_DEVCTL3_TARGET_LINK_WIDTH(devctl3)),
+ FLAG(devctl3, PCI_DEV3_DEVCTL3_UIO_MEM_RDWR_REQ_EN),
+ FLAG(~devctl3, PCI_DEV3_DEVCTL3_UIO_REQ_256B_DIS));
+
+ if (!config_fetch(d, where + PCI_DEV3_DEVSTA3, 2))
+ return;
+ devsta3 = get_conf_word(d, where + PCI_DEV3_DEVSTA3);
+
+ printf("\t\tDevSta3: Initial Link Width: %s, Segment Captured%c, Remote L0p%c\n",
+ link_width_str(buf, sizeof(buf), PCI_DEV3_DEVSTA3_INIT_LINK_WIDTH(devsta3)),
+ FLAG(devsta3, PCI_DEV3_DEVSTA3_SEGMENT_CAPTURED),
+ FLAG(devsta3, PCI_DEV3_DEVSTA3_REMOTE_L0P_SUPP));
+}
+
void
show_ext_caps(struct device *d, int type)
{
case PCI_EXT_CAP_ID_64GT:
cap_phy_64gt(d, where);
break;
+ case PCI_EXT_CAP_ID_DEV3:
+ cap_dev3(d, where);
+ break;
default:
printf("Extended Capability ID %#02x\n", id);
break;
--- /dev/null
+01:00.0 Non-Volatile memory controller: Synopsys EPMockUp (rev 03) (prog-if 02 [NVM Express])
+ Subsystem: Synopsys EPMockUp
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 43
+ IOMMU group: 14
+ Region 0: Memory at fc800000 (64-bit, non-prefetchable) [size=16K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [50] MSI: Enable- Count=1/8 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [70] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 75W
+ DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset-
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr+ TransPend-
+ LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <8us
+ ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s, Width x4
+ TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+
+ 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS- TPHComp- ExtTPHComp-
+ AtomicOpsCap: 32bit- 64bit- 128bitCAS-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled,
+ AtomicOpsCtl: ReqEn-
+ LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- Retimer- 2Retimers- DRS-
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
+ LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
+ EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
+ Retimer- 2Retimers- CrosslinkRes: unsupported
+ Capabilities: [b0] MSI-X: Enable+ Count=16 Masked-
+ Vector table: BAR=0 offset=00002000
+ PBA: BAR=0 offset=00002100
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+ AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
+ MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+ HeaderLog: 00000000 00000000 00000000 00000000
+ Capabilities: [158 v1] Secondary PCI Express
+ LnkCtl3: LnkEquIntrruptEn- PerformEqu-
+ LaneErrStat: 0
+ Capabilities: [178 v1] Latency Tolerance Reporting
+ Max snoop latency: 1048576ns
+ Max no snoop latency: 1048576ns
+ Capabilities: [180 v1] L1 PM Substates
+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
+ PortCommonModeRestoreTime=10us PortTPowerOnTime=10us
+ L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
+ T_CommonMode=0us LTR1.2_Threshold=32768ns
+ L1SubCtl2: T_PwrOn=10us
+ Kernel driver in use: nvme
+ Kernel modules: nvme
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--- /dev/null
+01:00.0 Non-Volatile memory controller: Synopsys EPMockUp (rev 03) (prog-if 02 [NVM Express])
+ Subsystem: Synopsys EPMockUp
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0, Cache Line Size: 64 bytes
+ Interrupt: pin A routed to IRQ 43
+ IOMMU group: 14
+ Region 0: Memory at fc800000 (64-bit, non-prefetchable) [size=16K]
+ Capabilities: [40] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [50] MSI: Enable- Count=1/8 Maskable+ 64bit+
+ Address: 0000000000000000 Data: 0000
+ Masking: 00000000 Pending: 00000000
+ Capabilities: [70] Express (v2) Endpoint, MSI 00
+ DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited
+ ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 75W
+ DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- FLReset-
+ MaxPayload 128 bytes, MaxReadReq 512 bytes
+ DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr+ TransPend-
+ LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <8us
+ ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
+ LnkSta: Speed 8GT/s, Width x4
+ TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+
+ 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS- TPHComp- ExtTPHComp-
+ AtomicOpsCap: 32bit- 64bit- 128bitCAS-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR+ 10BitTagReq- OBFF Disabled,
+ AtomicOpsCtl: ReqEn-
+ LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- Retimer- 2Retimers- DRS-
+ LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
+ Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+ Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot
+ LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+ EqualizationPhase1+
+ EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-
+ Retimer- 2Retimers- CrosslinkRes: unsupported
+ Capabilities: [b0] MSI-X: Enable+ Count=16 Masked-
+ Vector table: BAR=0 offset=00002000
+ PBA: BAR=0 offset=00002100
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
+ AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
+ MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+ HeaderLog: 00000000 00000000 00000000 00000000
+ Capabilities: [158 v1] Secondary PCI Express
+ LnkCtl3: LnkEquIntrruptEn- PerformEqu-
+ LaneErrStat: 0
+ Capabilities: [178 v1] Latency Tolerance Reporting
+ Max snoop latency: 1048576ns
+ Max no snoop latency: 1048576ns
+ Capabilities: [180 v1] L1 PM Substates
+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
+ PortCommonModeRestoreTime=10us PortTPowerOnTime=10us
+ L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-
+ T_CommonMode=0us LTR1.2_Threshold=32768ns
+ L1SubCtl2: T_PwrOn=10us
+ Kernel driver in use: nvme
+ Kernel modules: nvme
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projects / thirdparty / pciutils.git / commitdiff
