]> git.ipfire.org Git - thirdparty/openwrt.git/commitdiff
mediatek: dts: mt7981: add back #address-cells and #size-cells to eth node
authorShiji Yang <yangshiji66@outlook.com>
Fri, 8 Aug 2025 13:10:24 +0000 (21:10 +0800)
committerHauke Mehrtens <hauke@hauke-m.de>
Sun, 24 Aug 2025 11:22:09 +0000 (13:22 +0200)
They were lost when ported to the 6.12 kernel.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/19741
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
target/linux/mediatek/patches-6.12/117-complete-mt7981b-dtsi.patch

index 828fbc109b89dfde50f61c9af2e7d1862f97d1de..373938f1e4a583369aaefa8739bc61770237a6fc 100644 (file)
@@ -304,7 +304,7 @@ working:
                };
  
                efuse@11f20000 {
-@@ -211,17 +387,316 @@
+@@ -211,17 +387,318 @@
                        reg = <0 0x11f20000 0 0x1000>;
                        #address-cells = <1>;
                        #size-cells = <1>;
@@ -360,6 +360,8 @@ working:
 +              eth: ethernet@15100000 {
 +                      compatible = "mediatek,mt7981-eth";
 +                      reg = <0 0x15100000 0 0x80000>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
 +                      interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 +                                   <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 +                                   <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
@@ -623,7 +625,7 @@ working:
                        reg = <0 0x18000000 0 0x1000000>,
                              <0 0x10003000 0 0x1000>,
                              <0 0x11d10000 0 0x1000>;
-@@ -234,6 +709,67 @@
+@@ -234,6 +711,67 @@
                        clock-names = "mcu", "ap2conn";
                        resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
                        reset-names = "consys";
@@ -691,7 +693,7 @@ working:
                };
        };
  
-@@ -245,4 +781,8 @@
+@@ -245,4 +783,8 @@
                             <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
                             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
        };