re PR target/44751 (h8300 get_attr_cc warnings)

	PR target/44751
	* config/h8300/h8300.c: Include df.h.
	(push, pop): Use add_reg_note.
	(compute_plussi_cc, compute_logical_op_cc): Return enum attr_c.
	(compute_a_shift_cc): Likewise.
	(expand_a_shift): Argument code has type enum rtx_code.
	(struct shift_insn): Member cc_valid has type enum attr_cc.
	(struct shift_info) <cc_inline, cc_special>: Likewise.
	enum attr_cc.
	* config/h8300/h8300-protos.h (compute_plussi_cc): Update prototype.
	(compute_a_shift_cc, compute_logical_op_cc, expand_a_shift): Likewise.

From-SVN: r166336

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 54b448bbffdd11445a26d9414028f9ebc85a579a..f0fbbf41c9563e6283b2ef2df088af3501d52b14 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -117,6 +117,18 @@
        * genopinit.c (main) [FIXUNS_TRUNC_LIKE_FIX_TRUNC]: Cast
        iteration variables to enum machine_mode.
 
+       PR target/44751
+       * config/h8300/h8300.c: Include df.h.
+       (push, pop): Use add_reg_note.
+       (compute_plussi_cc, compute_logical_op_cc): Return enum attr_c.
+       (compute_a_shift_cc): Likewise.
+       (expand_a_shift): Argument code has type enum rtx_code.
+       (struct shift_insn): Member cc_valid has type enum attr_cc.
+       (struct shift_info) <cc_inline, cc_special>: Likewise.
+       enum attr_cc.
+       * config/h8300/h8300-protos.h (compute_plussi_cc): Update prototype.
+       (compute_a_shift_cc, compute_logical_op_cc, expand_a_shift): Likewise.
+
 2010-11-04  Ira Rosen  <irar@il.ibm.com>
 
        PR tree-optimization/46213

diff --git a/gcc/config/h8300/h8300-protos.h b/gcc/config/h8300/h8300-protos.h
index 676b3b7018e4186e9f4c9f887519058034bc6c81..1211c63897ab96ff83419975a202cbdb2b8b8a48 100644 (file)
--- a/gcc/config/h8300/h8300-protos.h
+++ b/gcc/config/h8300/h8300-protos.h
@@ -29,10 +29,8 @@ along with GCC; see the file COPYING3.  If not see
 extern unsigned int compute_mov_length (rtx *);
 extern const char *output_plussi (rtx *);
 extern unsigned int compute_plussi_length (rtx *);
-extern int compute_plussi_cc (rtx *);
 extern const char *output_a_shift (rtx *);
 extern unsigned int compute_a_shift_length (rtx, rtx *);
-extern int compute_a_shift_cc (rtx, rtx *);
 extern const char *output_a_rotate (enum rtx_code, rtx *);
 extern unsigned int compute_a_rotate_length (rtx *);
 extern const char *output_simode_bld (int, rtx[]);
@@ -44,10 +42,14 @@ extern void notice_update_cc (rtx, rtx);
 extern const char *output_logical_op (enum machine_mode, rtx *);
 extern unsigned int compute_logical_op_length (enum machine_mode,
                                               rtx *);
-extern int compute_logical_op_cc (enum machine_mode, rtx *);
+#ifdef HAVE_ATTR_cc
+extern enum attr_cc compute_plussi_cc (rtx *);
+extern enum attr_cc compute_a_shift_cc (rtx, rtx *);
+extern enum attr_cc compute_logical_op_cc (enum machine_mode, rtx *);
+#endif
 extern void h8300_expand_branch (rtx[]);
 extern void h8300_expand_store (rtx[]);
-extern bool expand_a_shift (enum machine_mode, int, rtx[]);
+extern bool expand_a_shift (enum machine_mode, enum rtx_code, rtx[]);
 extern int h8300_shift_needs_scratch_p (int, enum machine_mode);
 extern int expand_a_rotate (rtx[]);
 extern int fix_bit_operand (rtx *, enum rtx_code);

diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index f9bcc74732cb9f9828998ed4963fe6240ef0c510..2ab90fa24680e803d4d91b4918f34b1bc069d067 100644 (file)
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -45,6 +45,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "ggc.h"
 #include "target.h"
 #include "target-def.h"
+#include "df.h"
 
 /* Classifies a h8300_src_operand or h8300_dst_operand.
 
@@ -639,7 +640,7 @@ push (int rn)
   else
     x = gen_push_h8300hs_normal (reg);
   x = F (emit_insn (x), true);
-  REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
+  add_reg_note (x, REG_INC, stack_pointer_rtx);
 }
 
 /* Emit an insn to pop register RN.  */
@@ -657,7 +658,7 @@ pop (int rn)
   else
     x = gen_pop_h8300hs_normal (reg);
   x = emit_insn (x);
-  REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_INC, stack_pointer_rtx, 0);
+  add_reg_note (x, REG_INC, stack_pointer_rtx);
 }
 
 /* Emit an instruction to push or pop NREGS consecutive registers
@@ -3134,7 +3135,7 @@ compute_plussi_length (rtx *operands)
 
 /* Compute which flag bits are valid after an addition insn.  */
 
-int
+enum attr_cc
 compute_plussi_cc (rtx *operands)
 {
   enum machine_mode mode = GET_MODE (operands[0]);
@@ -3518,7 +3519,7 @@ compute_logical_op_length (enum machine_mode mode, rtx *operands)
 
 /* Compute which flag bits are valid after a logical insn.  */
 
-int
+enum attr_cc
 compute_logical_op_cc (enum machine_mode mode, rtx *operands)
 {
   /* Figure out the logical op that we need to perform.  */
@@ -3769,7 +3770,7 @@ output_h8sx_shift (rtx *operands, int suffix, int optype)
 /* Emit code to do shifts.  */
 
 bool
-expand_a_shift (enum machine_mode mode, int code, rtx operands[])
+expand_a_shift (enum machine_mode mode, enum rtx_code code, rtx operands[])
 {
   switch (h8sx_classify_shift (mode, code, operands[2]))
     {
@@ -3814,7 +3815,7 @@ enum shift_mode
 struct shift_insn
 {
   const char *const assembler;
-  const int cc_valid;
+  const enum attr_cc cc_valid;
 };
 
 /* Assembler instruction shift table.
@@ -3982,10 +3983,10 @@ struct shift_info {
   const char *shift2;
 
   /* CC status for SHIFT_INLINE.  */
-  int cc_inline;
+  enum attr_cc cc_inline;
 
   /* CC status  for SHIFT_SPECIAL.  */
-  int cc_special;
+  enum attr_cc cc_special;
 };
 
 static void get_shift_alg (enum shift_type,
@@ -4815,7 +4816,7 @@ compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
 
 /* Compute which flag bits are valid after a shift insn.  */
 
-int
+enum attr_cc
 compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
 {
   rtx shift = operands[3];