]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
pinctrl: rockchip: fix bank's pin_base computing
authorQuentin Schulz <quentin.schulz@cherry.de>
Fri, 31 Jan 2025 10:31:29 +0000 (11:31 +0100)
committerKever Yang <kever.yang@rock-chips.com>
Tue, 6 May 2025 07:59:43 +0000 (15:59 +0800)
The logic in the core reads the nr_pins of the controller and uses it as
the index of the first pin in the bank (pin_base) it currently parses.
It then increments the number of pins in the controller before going to
the next bank.

This works "fine" for controllers where nr_pins isn't defined in their
rockchip_pin_ctrl struct as it defaults to 0. However, when it is
already set, it'll make the index pin of each bank offset by the number
in nr_pins declared in the struct at initialization, and it'll keep
growing while adding banks, which means the total number of pins in the
controller will be misrepresented.

Additionally, U-Boot proper may probe this driver twice (pre-reloc and
true proper) and not reset nr_pins of the controller in-between meaning
the second probe will have an offset of the actual correct nr_pins.

Instead, let's just store locally the number of pins in the controller
and make sure it's reset between probes.

Finally, this stops modifying a const struct which will soon be
triggering a CPU abort at runtime.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
drivers/pinctrl/rockchip/pinctrl-rk3568.c
drivers/pinctrl/rockchip/pinctrl-rk3588.c
drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
drivers/pinctrl/rockchip/pinctrl-rockchip.h
drivers/pinctrl/rockchip/pinctrl-rv1126.c

index 5deedc648a41950461b6a468e4852fa0a5384207..c8a91b8bb6e925e0f2e7d6cd09f8a06a58be60dd 100644 (file)
@@ -345,7 +345,6 @@ static struct rockchip_pin_bank rk3568_pin_banks[] = {
 static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
        .pin_banks              = rk3568_pin_banks,
        .nr_banks               = ARRAY_SIZE(rk3568_pin_banks),
-       .nr_pins                = 160,
        .grf_mux_offset         = 0x0,
        .pmu_mux_offset         = 0x0,
        .iomux_routes           = rk3568_mux_route_data,
index 98ababc7c90700c4b27359fc3625519f20437306..fd8e617b9108c7314b8fdd4bbe1dfae71f1b6449 100644 (file)
@@ -324,7 +324,6 @@ static struct rockchip_pin_bank rk3588_pin_banks[] = {
 static const struct rockchip_pin_ctrl rk3588_pin_ctrl = {
        .pin_banks              = rk3588_pin_banks,
        .nr_banks               = ARRAY_SIZE(rk3588_pin_banks),
-       .nr_pins                = 160,
        .set_mux                = rk3588_set_mux,
        .set_pull               = rk3588_set_pull,
        .set_drive              = rk3588_set_drive,
index d449d07d32e74d1dec1978b1405bec94887908a2..4de67aba1c3453673891482babf2f009fa053a97 100644 (file)
@@ -532,6 +532,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
                        (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
        struct rockchip_pin_bank *bank;
        int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
+       u32 ctrl_nr_pins = 0;
 
        grf_offs = ctrl->grf_mux_offset;
        pmu_offs = ctrl->pmu_mux_offset;
@@ -543,8 +544,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d
                int bank_pins = 0;
 
                bank->priv = priv;
-               bank->pin_base = ctrl->nr_pins;
-               ctrl->nr_pins += bank->nr_pins;
+               bank->pin_base = ctrl_nr_pins;
+               ctrl_nr_pins += bank->nr_pins;
 
                /* calculate iomux and drv offsets */
                for (j = 0; j < 4; j++) {
index 5e3c9c90760266d1fe342cc2ef58afb5adeb8935..ba684baed24d3d0063c94d4bd16317f572c0aaa0 100644 (file)
@@ -503,7 +503,6 @@ struct rockchip_mux_route_data {
 struct rockchip_pin_ctrl {
        struct rockchip_pin_bank        *pin_banks;
        u32                             nr_banks;
-       u32                             nr_pins;
        int                             grf_mux_offset;
        int                             pmu_mux_offset;
        int                             grf_drv_offset;
index efa2408b204b421ad1c5a36b039d8c07c5b7237e..3878a5420dcc98f591e4eefadd78a2fe98b61c7e 100644 (file)
@@ -381,7 +381,6 @@ static struct rockchip_pin_bank rv1126_pin_banks[] = {
 static const struct rockchip_pin_ctrl rv1126_pin_ctrl = {
        .pin_banks              = rv1126_pin_banks,
        .nr_banks               = ARRAY_SIZE(rv1126_pin_banks),
-       .nr_pins                = 130,
        .grf_mux_offset         = 0x10004, /* mux offset from GPIO0_D0 */
        .pmu_mux_offset         = 0x0,
        .iomux_routes           = rv1126_mux_route_data,