riscv: starfive: jh7110: move uart0 clock frequency to config header

Move unnecessary clock frequency assignment out of device-tree and into the
board config header so that the ns16550 serial driver can successfully init
during SPL after failing to resolve the parent clock from upstream dts. The
serial driver will then resolve clock frequency from device-tree node parent
clock at init during Main app as it is expected by upstream.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi
index 6d85b2d91a7a5a6fd24a003a5f0ba9c41d221b90..049b0a7ce28fb62e128a06fa977452d030b2bc55 100644 (file)
--- a/arch/riscv/dts/jh7110-common-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi
@@ -27,7 +27,6 @@
        bootph-pre-ram;
        reg-offset = <0>;
        current-speed = <115200>;
-       clock-frequency = <24000000>;
 };
 
 &mmc0 {

diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h
index 049b0a0630164ad4a5039c15a827dcd165d7cc10..e7001b26abf0a75d65e0939c89867f3083fd7545 100644 (file)
--- a/include/configs/starfive-visionfive2.h
+++ b/include/configs/starfive-visionfive2.h
@@ -39,4 +39,6 @@
        "partitions=" PARTS_DEFAULT "\0" \
        "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
 
+#define CFG_SYS_NS16550_CLK            24000000
+
 #endif /* _STARFIVE_VISIONFIVE2_H */