iommu/amd: Add IO page fault notifier handler

Whenever there is a page fault IOMMU logs entry to ppr log and sends
interrupt to host. We have to handle the page fault and respond to IOMMU.

Add support to validate page fault request and hook it to core iommu
page fault handler.

Signed-off-by: Wei Huang <wei.huang2@amd.com>
Co-developed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Co-developed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20240418103400.6229-12-vasant.hegde@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>

diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 1a014dca7c2eb0352d5fb7d98fd3a58002502875..61ca32b7bb07f51575507da4c3177df3883a8409 100644 (file)
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -251,6 +251,14 @@
 #define PPR_ENTRY_SIZE         16
 #define PPR_LOG_SIZE           (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
 
+/* PAGE_SERVICE_REQUEST PPR Log Buffer Entry flags */
+#define PPR_FLAG_EXEC          0x002   /* Execute permission requested */
+#define PPR_FLAG_READ          0x004   /* Read permission requested */
+#define PPR_FLAG_WRITE         0x020   /* Write permission requested */
+#define PPR_FLAG_US            0x040   /* 1: User, 0: Supervisor */
+#define PPR_FLAG_RVSD          0x080   /* Reserved bit not zero */
+#define PPR_FLAG_GN            0x100   /* GVA and PASID is valid */
+
 #define PPR_REQ_TYPE(x)                (((x) >> 60) & 0xfULL)
 #define PPR_FLAGS(x)           (((x) >> 48) & 0xfffULL)
 #define PPR_DEVID(x)           ((x) & 0xffffULL)

diff --git a/drivers/iommu/amd/ppr.c b/drivers/iommu/amd/ppr.c
index a33ce537b76ee10a067fbac7b6e3f868fee11593..9bdd1db5f60a8c0af2aaddb20229b7ed90417712 100644 (file)
--- a/drivers/iommu/amd/ppr.c
+++ b/drivers/iommu/amd/ppr.c
@@ -60,6 +60,103 @@ void amd_iommu_restart_ppr_log(struct amd_iommu *iommu)
                              MMIO_STATUS_PPR_OVERFLOW_MASK);
 }
 
+static inline u32 ppr_flag_to_fault_perm(u16 flag)
+{
+       int perm = 0;
+
+       if (flag & PPR_FLAG_READ)
+               perm |= IOMMU_FAULT_PERM_READ;
+       if (flag & PPR_FLAG_WRITE)
+               perm |= IOMMU_FAULT_PERM_WRITE;
+       if (flag & PPR_FLAG_EXEC)
+               perm |= IOMMU_FAULT_PERM_EXEC;
+       if (!(flag & PPR_FLAG_US))
+               perm |= IOMMU_FAULT_PERM_PRIV;
+
+       return perm;
+}
+
+static bool ppr_is_valid(struct amd_iommu *iommu, u64 *raw)
+{
+       struct device *dev = iommu->iommu.dev;
+       u16 devid = PPR_DEVID(raw[0]);
+
+       if (!(PPR_FLAGS(raw[0]) & PPR_FLAG_GN)) {
+               dev_dbg(dev, "PPR logged [Request ignored due to GN=0 (device=%04x:%02x:%02x.%x "
+                       "pasid=0x%05llx address=0x%llx flags=0x%04llx tag=0x%03llx]\n",
+                       iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
+                       PPR_PASID(raw[0]), raw[1], PPR_FLAGS(raw[0]), PPR_TAG(raw[0]));
+               return false;
+       }
+
+       if (PPR_FLAGS(raw[0]) & PPR_FLAG_RVSD) {
+               dev_dbg(dev, "PPR logged [Invalid request format (device=%04x:%02x:%02x.%x "
+                       "pasid=0x%05llx address=0x%llx flags=0x%04llx tag=0x%03llx]\n",
+                       iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
+                       PPR_PASID(raw[0]), raw[1], PPR_FLAGS(raw[0]), PPR_TAG(raw[0]));
+               return false;
+       }
+
+       return true;
+}
+
+static void iommu_call_iopf_notifier(struct amd_iommu *iommu, u64 *raw)
+{
+       struct iommu_dev_data *dev_data;
+       struct iopf_fault event;
+       struct pci_dev *pdev;
+       u16 devid = PPR_DEVID(raw[0]);
+
+       if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
+               pr_info_ratelimited("Unknown PPR request received\n");
+               return;
+       }
+
+       pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id,
+                                          PCI_BUS_NUM(devid), devid & 0xff);
+       if (!pdev)
+               return;
+
+       if (!ppr_is_valid(iommu, raw))
+               goto out;
+
+       memset(&event, 0, sizeof(struct iopf_fault));
+
+       event.fault.type = IOMMU_FAULT_PAGE_REQ;
+       event.fault.prm.perm = ppr_flag_to_fault_perm(PPR_FLAGS(raw[0]));
+       event.fault.prm.addr = (u64)(raw[1] & PAGE_MASK);
+       event.fault.prm.pasid = PPR_PASID(raw[0]);
+       event.fault.prm.grpid = PPR_TAG(raw[0]) & 0x1FF;
+
+       /*
+        * PASID zero is used for requests from the I/O device without
+        * a PASID
+        */
+       dev_data = dev_iommu_priv_get(&pdev->dev);
+       if (event.fault.prm.pasid == 0 ||
+           event.fault.prm.pasid >= dev_data->max_pasids) {
+               pr_info_ratelimited("Invalid PASID : 0x%x, device : 0x%x\n",
+                                   event.fault.prm.pasid, pdev->dev.id);
+               goto out;
+       }
+
+       event.fault.prm.flags |= IOMMU_FAULT_PAGE_RESPONSE_NEEDS_PASID;
+       event.fault.prm.flags |= IOMMU_FAULT_PAGE_REQUEST_PASID_VALID;
+       if (PPR_TAG(raw[0]) & 0x200)
+               event.fault.prm.flags |= IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE;
+
+       /* Submit event */
+       iommu_report_device_fault(&pdev->dev, &event);
+
+       return;
+
+out:
+       /* Nobody cared, abort */
+       amd_iommu_complete_ppr(&pdev->dev, PPR_PASID(raw[0]),
+                              IOMMU_PAGE_RESP_FAILURE,
+                              PPR_TAG(raw[0]) & 0x1FF);
+}
+
 void amd_iommu_poll_ppr_log(struct amd_iommu *iommu)
 {
        u32 head, tail;
@@ -105,7 +202,8 @@ void amd_iommu_poll_ppr_log(struct amd_iommu *iommu)
                head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
                writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
 
-               /* TODO: PPR Handler will be added when we add IOPF support */
+               /* Handle PPR entry */
+               iommu_call_iopf_notifier(iommu, entry);
        }
 }