6.1-stable patches

added patches:
	drm-i915-split-icl_color_commit_noarm-from-skl_color_commit_noarm.patch
	drm-i915-use-_mmio_pipe-for-skl_bottom_color.patch

diff --git a/queue-6.1/drm-i915-split-icl_color_commit_noarm-from-skl_color_commit_noarm.patch b/queue-6.1/drm-i915-split-icl_color_commit_noarm-from-skl_color_commit_noarm.patch
new file mode 100644 (file)
index 0000000..f137c3d
--- /dev/null
+++ b/queue-6.1/drm-i915-split-icl_color_commit_noarm-from-skl_color_commit_noarm.patch
@@ -0,0 +1,70 @@
+From 76b767d4d1cd052e455cf18e06929e8b2b70101d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Mon, 20 Mar 2023 11:54:33 +0200
+Subject: drm/i915: Split icl_color_commit_noarm() from skl_color_commit_noarm()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 76b767d4d1cd052e455cf18e06929e8b2b70101d upstream.
+
+We're going to want different behavior for skl/glk vs. icl
+in .color_commit_noarm(), so split the hook into two. Arguably
+we already had slightly different behaviour since
+csc_enable/gamma_enable are never set on icl+, so the old
+code was perhaps a bit confusing as well.
+
+Cc: <stable@vger.kernel.org> #v5.19+
+Cc: Manasi Navare <navaremanasi@google.com>
+Cc: Drew Davenport <ddavenport@chromium.org>
+Cc: Imre Deak <imre.deak@intel.com>
+Cc: Jouni Högander <jouni.hogander@intel.com>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20230320095438.17328-2-ville.syrjala@linux.intel.com
+Reviewed-by: Imre Deak <imre.deak@intel.com>
+(cherry picked from commit f161eb01f50ab31f2084975b43bce54b7b671e17)
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_color.c |   21 ++++++++++++++++++++-
+ 1 file changed, 20 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_color.c
++++ b/drivers/gpu/drm/i915/display/intel_color.c
+@@ -2098,6 +2098,25 @@ static void glk_read_luts(struct intel_c
+       }
+ }
+ 
++static void icl_color_commit_arm(const struct intel_crtc_state *crtc_state)
++{
++      struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
++      struct drm_i915_private *i915 = to_i915(crtc->base.dev);
++      enum pipe pipe = crtc->pipe;
++
++      /*
++       * We don't (yet) allow userspace to control the pipe background color,
++       * so force it to black.
++       */
++      intel_de_write(i915, SKL_BOTTOM_COLOR(pipe), 0);
++
++      intel_de_write(i915, GAMMA_MODE(crtc->pipe),
++                     crtc_state->gamma_mode);
++
++      intel_de_write_fw(i915, PIPE_CSC_MODE(crtc->pipe),
++                        crtc_state->csc_mode);
++}
++
+ static struct drm_property_blob *
+ icl_read_lut_multi_segment(struct intel_crtc *crtc)
+ {
+@@ -2183,7 +2202,7 @@ static const struct intel_color_funcs i9
+ static const struct intel_color_funcs icl_color_funcs = {
+       .color_check = icl_color_check,
+       .color_commit_noarm = icl_color_commit_noarm,
+-      .color_commit_arm = skl_color_commit_arm,
++      .color_commit_arm = icl_color_commit_arm,
+       .load_luts = icl_load_luts,
+       .read_luts = icl_read_luts,
+ };

diff --git a/queue-6.1/drm-i915-use-_mmio_pipe-for-skl_bottom_color.patch b/queue-6.1/drm-i915-use-_mmio_pipe-for-skl_bottom_color.patch
new file mode 100644 (file)
index 0000000..832f467
--- /dev/null
+++ b/queue-6.1/drm-i915-use-_mmio_pipe-for-skl_bottom_color.patch
@@ -0,0 +1,38 @@
+From 05ca98523481aa687c5a8dce8939fec539632153 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Wed, 26 Oct 2022 14:38:57 +0300
+Subject: drm/i915: Use _MMIO_PIPE() for SKL_BOTTOM_COLOR
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 05ca98523481aa687c5a8dce8939fec539632153 upstream.
+
+No need to use _MMIO_PIPE2() for SKL_BOTTOM_COLOR
+since all pipe registers are evenly spread on skl+.
+Switch to _MMIO_PIPE() and thus avoid the hidden dev_priv.
+
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20221026113906.10551-3-ville.syrjala@linux.intel.com
+Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/i915_reg.h |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -3747,9 +3747,10 @@
+ 
+ /* Skylake+ pipe bottom (background) color */
+ #define _SKL_BOTTOM_COLOR_A           0x70034
++#define _SKL_BOTTOM_COLOR_B           0x71034
+ #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE               REG_BIT(31)
+ #define   SKL_BOTTOM_COLOR_CSC_ENABLE         REG_BIT(30)
+-#define SKL_BOTTOM_COLOR(pipe)                _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
++#define SKL_BOTTOM_COLOR(pipe)                _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
+ 
+ #define _ICL_PIPE_A_STATUS                    0x70058
+ #define ICL_PIPESTATUS(pipe)                  _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)

diff --git a/queue-6.1/series b/queue-6.1/series
index ca026fcaeceb9b3443ccb57f2410e93bf1fbea48..226e17528897f7dd48ee1f88370a8f9d92f5591a 100644 (file)
--- a/queue-6.1/series
+++ b/queue-6.1/series
@@ -146,3 +146,5 @@ drm-amdgpu-skip-psp-suspend-for-imu-enabled-asics-mode2-reset.patch
 drm-display-dp_mst-handle-old-new-payload-states-in-drm_dp_remove_payload.patch
 drm-i915-dp_mst-fix-payload-removal-during-output-disabling.patch
 drm-bridge-lt9611-fix-pll-being-unable-to-lock.patch
+drm-i915-use-_mmio_pipe-for-skl_bottom_color.patch
+drm-i915-split-icl_color_commit_noarm-from-skl_color_commit_noarm.patch