RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM

We extend the KVM ISA extension ONE_REG interface to allow VMM tools to
detect and enable Svade and Svadu extensions for Guest/VM. Since the
henvcfg.ADUE is read-only zero if the menvcfg.ADUE is zero, the Svadu
extension is available for Guest/VM and the Svade extension is allowed
to disabledonly when arch_has_hw_pte_young() is true.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20240726084931.28924-4-yongxuan.wang@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org>

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index e97db3296456e19f79ca02e4c4f70ae1b4abb48b..85bbc472989dffe73c5a96716397002ebef40596 100644 (file)
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -175,6 +175,8 @@ enum KVM_RISCV_ISA_EXT_ID {
        KVM_RISCV_ISA_EXT_ZCF,
        KVM_RISCV_ISA_EXT_ZCMOP,
        KVM_RISCV_ISA_EXT_ZAWRS,
+       KVM_RISCV_ISA_EXT_SVADE,
+       KVM_RISCV_ISA_EXT_SVADU,
        KVM_RISCV_ISA_EXT_MAX,
 };
 

diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index dc3f76f6e46ceafb25c88763e310db622715a447..e048dcc6e65e73c03232cb327ae9c85a16aede1f 100644 (file)
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -551,6 +551,10 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu)
        if (riscv_isa_extension_available(isa, ZICBOZ))
                cfg->henvcfg |= ENVCFG_CBZE;
 
+       if (riscv_isa_extension_available(isa, SVADU) &&
+           !riscv_isa_extension_available(isa, SVADE))
+               cfg->henvcfg |= ENVCFG_ADUE;
+
        if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
                cfg->hstateen0 |= SMSTATEEN0_HSENVCFG;
                if (riscv_isa_extension_available(isa, SSAIA))

diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
index b319c4c13c54ce22d2a7552f4c9f256a0c50780e..b3f58908902a7487114b5d2acbd6ac99bc61769d 100644 (file)
--- a/arch/riscv/kvm/vcpu_onereg.c
+++ b/arch/riscv/kvm/vcpu_onereg.c
@@ -15,6 +15,7 @@
 #include <asm/cacheflush.h>
 #include <asm/cpufeature.h>
 #include <asm/kvm_vcpu_vector.h>
+#include <asm/pgtable.h>
 #include <asm/vector.h>
 
 #define KVM_RISCV_BASE_ISA_MASK                GENMASK(25, 0)
@@ -38,6 +39,8 @@ static const unsigned long kvm_isa_ext_arr[] = {
        KVM_ISA_EXT_ARR(SSAIA),
        KVM_ISA_EXT_ARR(SSCOFPMF),
        KVM_ISA_EXT_ARR(SSTC),
+       KVM_ISA_EXT_ARR(SVADE),
+       KVM_ISA_EXT_ARR(SVADU),
        KVM_ISA_EXT_ARR(SVINVAL),
        KVM_ISA_EXT_ARR(SVNAPOT),
        KVM_ISA_EXT_ARR(SVPBMT),
@@ -110,6 +113,12 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext)
        case KVM_RISCV_ISA_EXT_SSCOFPMF:
                /* Sscofpmf depends on interrupt filtering defined in ssaia */
                return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA);
+       case KVM_RISCV_ISA_EXT_SVADU:
+               /*
+                * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
+                * Guest OS can use Svadu only when host OS enable Svadu.
+                */
+               return arch_has_hw_pte_young();
        case KVM_RISCV_ISA_EXT_V:
                return riscv_v_vstate_ctrl_user_allowed();
        default:
@@ -181,6 +190,12 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
        /* Extensions which can be disabled using Smstateen */
        case KVM_RISCV_ISA_EXT_SSAIA:
                return riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN);
+       case KVM_RISCV_ISA_EXT_SVADE:
+               /*
+                * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
+                * Svade is not allowed to disable when the platform use Svade.
+                */
+               return arch_has_hw_pte_young();
        default:
                break;
        }