Arm: Fix thumb2 PLT branch offsets.

When I previously changed these offsets I had incorrectly used an offset of -2
for this Thumb2 PLT.  Unfortunately because we had no tests for this PLT I had
missed that the result was incorrect.

This patch fixes the offset to PC .-4 so that it correctly addresses the
previous instruction and adds a test for this PLT stub.

bfd/ChangeLog:

	* elf32-arm.c (elf32_thumb2_plt_entry): Fix PC-rel offset.

ld/ChangeLog:

	* testsuite/ld-arm/arm-elf.exp (thumb-plt): New.
	* testsuite/ld-arm/thumb-plt.d: New test.
	* testsuite/ld-arm/thumb-plt.s: New test.

(cherry picked from commit 15ccbdd717530f81f545a716f0df1de62aee1157)
(cherry picked from commit 3ce23ca1de4c769c4b7247f0724a10ef5fb24a11)

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 062b7ec8734ba241c987754f2d0debfde93db3af..826e876acd1ed005b26e4681a545f9b3222b5d0e 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,10 @@
+2020-04-08  Tamar Christina  <tamar.christina@arm.com>
+
+       Backport from mainline.
+       2020-04-01  Tamar Christina  <tamar.christina@arm.com>
+
+       * elf32-arm.c (elf32_thumb2_plt_entry): Fix PC-rel offset.
+
 2020-03-30  Alan Modra  <amodra@gmail.com>
 
        PR 25745

diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index faf8376f2006f9c8f8da977fd5341741af84ecd5..bf5095a5cf4572395bf6444df8865b16cd7a3881 100644 (file)
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -2453,8 +2453,8 @@ static const bfd_vma elf32_thumb2_plt_entry [] =
   0x0c00f240,          /* movw    ip, #0xNNNN    */
   0x0c00f2c0,          /* movt    ip, #0xNNNN    */
   0xf8dc44fc,          /* add     ip, pc         */
-  0xe7fdf000           /* ldr.w   pc, [ip]       */
-                       /* b      .-2             */
+  0xe7fcf000           /* ldr.w   pc, [ip]       */
+                       /* b      .-4             */
 };
 
 /* The format of the first entry in the procedure linkage table

diff --git a/ld/ChangeLog b/ld/ChangeLog
index 35e6ccbcd7328fbf10918b92686f77c145ade3e5..62f2f332a992f55dfee0317b2ab7ea1952ac40de 100644 (file)
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-08  Tamar Christina  <tamar.christina@arm.com>
+
+       Backport from mainline.
+       2020-04-01  Tamar Christina  <tamar.christina@arm.com>
+
+       * testsuite/ld-arm/arm-elf.exp (thumb-plt): New.
+       * testsuite/ld-arm/thumb-plt.d: New test.
+       * testsuite/ld-arm/thumb-plt.s: New test.
+
 2020-03-25  H.J. Lu  <hongjiu.lu@intel.com>
 
        * testsuite/ld-plugin/lto.exp (lto_link_tests): Run PR ld/25355

diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index 44e599f4be3d3b5c80c7e57adb6c847f8b80f0e8..a44ef36f6c8ee857ce14a752521e4e75e1a02d20 100644 (file)
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -1261,3 +1261,7 @@ set arm_unwind_tests {
      "unwind-mix"}
 }
 run_ld_link_tests $arm_unwind_tests
+
+if { ![istarget "arm*-*-nacl*"] } {
+    run_dump_test "thumb-plt"
+}

diff --git a/ld/testsuite/ld-arm/thumb-plt.d b/ld/testsuite/ld-arm/thumb-plt.d
new file mode 100644 (file)
index 0000000..441325b
--- /dev/null
+++ b/ld/testsuite/ld-arm/thumb-plt.d
@@ -0,0 +1,34 @@
+#source: thumb-plt.s
+#name: Thumb only PLT and GOT
+#ld: -shared -e0
+#objdump: -dr
+#skip: *-*-pe *-*-wince *-*-vxworks armeb-*-* *-*-gnueabihf
+
+.*: +file format .*arm.*
+
+
+Disassembly of section \.plt:
+
+00000110 <\.plt>:
+ 110:  b500            push    {lr}
+ 112:  f8df e008       ldr.w   lr, \[pc, #8\]  ; 11c <\.plt\+0xc>
+ 116:  44fe            add     lr, pc
+ 118:  f85e ff08       ldr.w   pc, \[lr, #8\]!
+ 11c:  0001009c        \.word  0x0001009c
+
+00000120 <foo@plt>:
+ 120:  f240 0c98       movw    ip, #152        ; 0x98
+ 124:  f2c0 0c01       movt    ip, #1
+ 128:  44fc            add     ip, pc
+ 12a:  f8dc f000       ldr.w   pc, \[ip\]
+ 12e:  e7fc            b.n     12a <foo@plt\+0xa>
+
+Disassembly of section .text:
+
+00000130 <bar>:
+ 130:  b580            push    {r7, lr}
+ 132:  af00            add     r7, sp, #0
+ 134:  f7ff fff4       bl      120 <foo@plt>
+ 138:  4603            mov     r3, r0
+ 13a:  4618            mov     r0, r3
+ 13c:  bd80            pop     {r7, pc}

diff --git a/ld/testsuite/ld-arm/thumb-plt.s b/ld/testsuite/ld-arm/thumb-plt.s
new file mode 100644 (file)
index 0000000..e3fd80f
--- /dev/null
+++ b/ld/testsuite/ld-arm/thumb-plt.s
@@ -0,0 +1,18 @@
+       .cpu cortex-m3
+       .text
+       .align  1
+       .global bar
+       .arch armv7-m
+       .syntax unified
+       .thumb
+       .thumb_func
+       .fpu softvfp
+       .type   bar, %function
+bar:
+       push    {r7, lr}
+       add     r7, sp, #0
+       bl      foo(PLT)
+       mov     r3, r0
+       mov     r0, r3
+       pop     {r7, pc}
+       .size   bar, .-bar