KVM: arm64: Make the exposed feature bits in AA64DFR0_EL1 writable from userspace

KVM exposes the OS double lock feature bit to Guests but returns
RAZ/WI on Guest OSDLR_EL1 access. This breaks Guest migration between
systems where this feature differ. Add support to make this feature
writable from userspace by setting the mask bit. While at it, set the
mask bits for the exposed WRPs(Number of Watchpoints) as well.
Also update the selftest to cover these fields.

However we still can't make BRPs and CTX_CMPs fields writable, because
as per ARM ARM DDI 0487K.a, section D2.8.3 Breakpoint types and
linking of breakpoints, highest numbered breakpoints(BRPs) must be
context aware breakpoints(CTX_CMPs). KVM does not trap + emulate the
breakpoint registers, and as such cannot support a layout that misaligns
with the underlying hardware.

Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
Link: https://lore.kernel.org/r/20240816132819.34316-1-shameerali.kolothum.thodi@huawei.com
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c90324060436b272fd0f7dde8e023a7911edcc7b..5a49e8331fbf587472d53f7adc7448242a254228 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -2376,7 +2376,21 @@ static const struct sys_reg_desc sys_reg_descs[] = {
          .get_user = get_id_reg,
          .set_user = set_id_aa64dfr0_el1,
          .reset = read_sanitised_id_aa64dfr0_el1,
-         .val = ID_AA64DFR0_EL1_PMUVer_MASK |
+       /*
+        * Prior to FEAT_Debugv8.9, the architecture defines context-aware
+        * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs).
+        * KVM does not trap + emulate the breakpoint registers, and as such
+        * cannot support a layout that misaligns with the underlying hardware.
+        * While it may be possible to describe a subset that aligns with
+        * hardware, just prevent changes to BRPs and CTX_CMPs altogether for
+        * simplicity.
+        *
+        * See DDI0487K.a, section D2.8.3 Breakpoint types and linking
+        * of breakpoints for more details.
+        */
+         .val = ID_AA64DFR0_EL1_DoubleLock_MASK |
+                ID_AA64DFR0_EL1_WRPs_MASK |
+                ID_AA64DFR0_EL1_PMUVer_MASK |
                 ID_AA64DFR0_EL1_DebugVer_MASK, },
        ID_SANITISED(ID_AA64DFR1_EL1),
        ID_UNALLOCATED(5,2),

diff --git a/tools/testing/selftests/kvm/aarch64/set_id_regs.c b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
index d20981663831f4cfd2a8027fc605e8054e3add2a..6edc5412abe8f78dfd1be149ec9fcda4786a75a9 100644 (file)
--- a/tools/testing/selftests/kvm/aarch64/set_id_regs.c
+++ b/tools/testing/selftests/kvm/aarch64/set_id_regs.c
@@ -68,6 +68,8 @@ struct test_feature_reg {
        }
 
 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
+       S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0),
+       REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0),
        S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
        REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP),
        REG_FTR_END,