--- /dev/null
+From fea92cbf0850d788683827990670d3968f893327 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Sun, 20 Jan 2013 21:55:22 +0100
+Subject: ath9k: allow setting arbitrary antenna masks on AR9003+
+
+From: Felix Fietkau <nbd@openwrt.org>
+
+commit fea92cbf0850d788683827990670d3968f893327 upstream.
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+Signed-off-by: John W. Linville <linville@tuxdriver.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/net/wireless/ath/ath9k/main.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/net/wireless/ath/ath9k/main.c
++++ b/drivers/net/wireless/ath/ath9k/main.c
+@@ -1830,6 +1830,9 @@ static u32 fill_chainmask(u32 cap, u32 n
+
+ static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
+ {
++ if (AR_SREV_9300_20_OR_LATER(ah))
++ return true;
++
+ switch (val & 0x7) {
+ case 0x1:
+ case 0x3:
--- /dev/null
+From 24171dd92096fc370b195f3f6bdc0798855dc3f9 Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@openwrt.org>
+Date: Sun, 20 Jan 2013 21:55:21 +0100
+Subject: ath9k_hw: fix chain swap setting when setting rx chainmask to 5
+
+From: Felix Fietkau <nbd@openwrt.org>
+
+commit 24171dd92096fc370b195f3f6bdc0798855dc3f9 upstream.
+
+Chain swapping should only be enabled when the EEPROM chainmask is set to 5,
+regardless of what the runtime chainmask is.
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+Signed-off-by: John W. Linville <linville@tuxdriver.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/net/wireless/ath/ath9k/ar9003_phy.c | 25 ++++++-------------------
+ 1 file changed, 6 insertions(+), 19 deletions(-)
+
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+@@ -588,30 +588,17 @@ static void ar9003_hw_init_bb(struct ath
+
+ static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
+ {
+- switch (rx) {
+- case 0x5:
++ if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
+ REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
+ AR_PHY_SWAP_ALT_CHAIN);
+- case 0x3:
+- case 0x1:
+- case 0x2:
+- case 0x7:
+- REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
+- REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
+- break;
+- default:
+- break;
+- }
++
++ REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
++ REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
+
+ if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
+- REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
+- else
+- REG_WRITE(ah, AR_SELFGEN_MASK, tx);
++ tx = 3;
+
+- if (tx == 0x5) {
+- REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
+- AR_PHY_SWAP_ALT_CHAIN);
+- }
++ REG_WRITE(ah, AR_SELFGEN_MASK, tx);
+ }
+
+ /*