"(du1_power4+du2_power4+du3_power4+du4_power4),\
iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4")
-(define_insn_reservation "power4-load-update-indexed" 4 ; 3
+(define_insn_reservation "power4-load-update-indexed" 3
(and (eq_attr "type" "load_ux")
(eq_attr "cpu" "power4"))
"du1_power4+du2_power4+du3_power4+du4_power4,\
(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
-(define_insn_reservation "power4-lmul-cmp" 8 ; 7
+(define_insn_reservation "power4-lmul-cmp" 7
(and (eq_attr "type" "lmul_compare")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4,iu1_power4*6,iu2_power4)\
(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
-(define_insn_reservation "power4-imul-cmp" 6 ; 5
+(define_insn_reservation "power4-imul-cmp" 5
(and (eq_attr "type" "imul_compare")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4,iu1_power4*4,iu2_power4)\
(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr")
-(define_insn_reservation "power4-lmul" 8 ; 7
+(define_insn_reservation "power4-lmul" 7
(and (eq_attr "type" "lmul")
(eq_attr "cpu" "power4"))
"(du1_power4,iu1_power4*6)\
; |(du3_power4,nothing,iu2_power4*6)\
; |(du4_power4,nothing,iu2_power4*6)")
-(define_insn_reservation "power4-imul" 6 ; 5
+(define_insn_reservation "power4-imul" 5
(and (eq_attr "type" "imul")
(eq_attr "cpu" "power4"))
"(du1_power4,iu1_power4*4)\
; |(du3_power4,nothing,iu2_power4*4)\
; |(du4_power4,nothing,iu1_power4*4)")
-(define_insn_reservation "power4-imul3" 5 ; 4
+(define_insn_reservation "power4-imul3" 4
(and (eq_attr "type" "imul2,imul3")
(eq_attr "cpu" "power4"))
"(du1_power4,iu1_power4*3)\
"du1_power4,iu1_power4")
; Basic FP latency is 6 cycles
-(define_insn_reservation "power4-fp" 7 ; 6
+(define_insn_reservation "power4-fp" 6
(and (eq_attr "type" "fp,dmul")
(eq_attr "cpu" "power4"))
"fpq_power4")
offset1 = 0;
}
- /* Make sure the second address is a (mem (plus (reg) (const_int))). */
+/* Make sure the second address is a (mem (plus (reg) (const_int)))
+ or if it is (mem (reg)) then make sure that offset1 is -8 and the same
+ register as addr1. */
+ if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
+ return 1;
if (GET_CODE (addr2) != PLUS)
return 0;
case PROCESSOR_POWER4:
*total = (GET_CODE (XEXP (x, 1)) != CONST_INT
? GET_MODE (XEXP (x, 1)) != DImode
- ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7)
- : COSTS_N_INSNS (4));
+ ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)
+ : COSTS_N_INSNS (2));
return true;
default:
case PROCESSOR_PPC620:
case PROCESSOR_PPC630:
- case PROCESSOR_POWER4:
*total = (GET_MODE (XEXP (x, 1)) != DImode
? COSTS_N_INSNS (21)
: COSTS_N_INSNS (37));
*total = COSTS_N_INSNS (23);
return true;
+ case PROCESSOR_POWER4:
+ *total = (GET_MODE (XEXP (x, 1)) != DImode
+ ? COSTS_N_INSNS (18)
+ : COSTS_N_INSNS (34));
+ return true;
+
default:
abort ();
}