-Tue Jun 25 20:59:56 2002 J"orn Rennecke <joern.rennecke@superh.com>
+Tue Jun 25 21:51:13 2002 J"orn Rennecke <joern.rennecke@superh.com>
+
+ * optabs.c (expand_vector_binop, expand_vector_unop): Don't assume
+ GET_MODE_UNIT_SIZE (mode) == UNITS_PER_WORD.
* config/sh/lib1funcs.asm (udivdi3): Make first divide step
produce a 32 bit result before normalization, then normalize with a
enum optab_methods methods;
{
enum machine_mode submode;
- int elts, i;
+ int elts, subsize, i;
rtx t, a, b, res, seq;
enum mode_class class;
class = GET_MODE_CLASS (mode);
submode = GET_MODE_INNER (mode);
+ subsize = GET_MODE_UNIT_SIZE (mode);
elts = GET_MODE_NUNITS (mode);
if (!target)
for (i = 0; i < elts; ++i)
{
t = simplify_gen_subreg (submode, target, mode,
- i * UNITS_PER_WORD);
+ i * subsize);
a = simplify_gen_subreg (submode, op0, mode,
- i * UNITS_PER_WORD);
+ i * subsize);
b = simplify_gen_subreg (submode, op1, mode,
- i * UNITS_PER_WORD);
+ i * subsize);
if (binoptab->code == DIV)
{
int unsignedp;
{
enum machine_mode submode;
- int elts, i;
+ int elts, subsize, i;
rtx t, a, res, seq;
submode = GET_MODE_INNER (mode);
+ subsize = GET_MODE_UNIT_SIZE (mode);
elts = GET_MODE_NUNITS (mode);
if (!target)
for (i = 0; i < elts; ++i)
{
- t = simplify_gen_subreg (submode, target, mode, i * UNITS_PER_WORD);
- a = simplify_gen_subreg (submode, op0, mode, i * UNITS_PER_WORD);
+ t = simplify_gen_subreg (submode, target, mode, i * subsize);
+ a = simplify_gen_subreg (submode, op0, mode, i * subsize);
res = expand_unop (submode, unoptab, a, t, unsignedp);
+Tue Jun 25 21:50:38 2002 J"orn Rennecke <joern.rennecke@superh.com>
+
+ * gcc.c-torture/execute/simd-2.c: New test.
+
2002-06-25 Neil Booth <neil@daikokuya.co.uk>
* gcc.dg/cpp/mi7.c, gcc.dg/cpp/mi7a.h, gcc.dg/cpp/mi7b.h,
--- /dev/null
+/*
+ Purpose: Test generic SIMD support, V8HImode. This test should work
+ regardless of if the target has SIMD instructions.
+*/
+
+typedef int __attribute__((mode(V8HI))) vecint;
+
+vecint i = { 150, 100, 150, 200 };
+vecint j = { 10, 13, 20, 30 };
+vecint k;
+
+union {
+ vecint v;
+ short i[8];
+} res;
+
+/* This should go away once we can use == and != on vector types. */
+void
+verify (int a1, int a2, int a3, int a4,
+ int b1, int b2, int b3, int b4)
+{
+ if (a1 != b1
+ || a2 != b2
+ || a3 != b3
+ || a4 != b4)
+ abort ();
+}
+
+int
+main ()
+{
+ k = i + j;
+ res.v = k;
+
+ verify (res.i[0], res.i[1], res.i[2], res.i[3], 160, 113, 170, 230);
+
+ k = i * j;
+ res.v = k;
+
+ verify (res.i[0], res.i[1], res.i[2], res.i[3], 1500, 1300, 3000, 6000);
+
+ k = i / j;
+ res.v = k;
+
+ verify (res.i[0], res.i[1], res.i[2], res.i[3], 15, 7, 7, 6);
+
+ k = -i;
+ res.v = k;
+ verify (res.i[0], res.i[1], res.i[2], res.i[3],
+ -150, -100, -150, -200);
+
+ exit (0);
+}