]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915/psr: Add intel_psr2_panic_force_full_update
authorJocelyn Falempe <jfalempe@redhat.com>
Tue, 24 Jun 2025 09:01:20 +0000 (11:01 +0200)
committerMaarten Lankhorst <dev@lankhorst.se>
Fri, 27 Jun 2025 09:48:23 +0000 (11:48 +0200)
When the panic handler is called, configure the psr to send the full
framebuffer to the monitor, otherwise the panic screen is only
partially visible.

Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://lore.kernel.org/r/20250624091501.257661-12-jfalempe@redhat.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
drivers/gpu/drm/i915/display/intel_plane.c
drivers/gpu/drm/i915/display/intel_psr.c
drivers/gpu/drm/i915/display/intel_psr.h

index de6d10d8f1faf3b04c81ff2bb70dc4c8fbfa1513..36fb07471deb4b74e2be80fae3995460cd640110 100644 (file)
@@ -58,6 +58,7 @@
 #include "intel_fb_pin.h"
 #include "intel_fbdev.h"
 #include "intel_plane.h"
+#include "intel_psr.h"
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
 #include "skl_watermark.h"
@@ -1320,6 +1321,7 @@ static unsigned int intel_4tile_get_offset(unsigned int width, unsigned int x, u
 static void intel_panic_flush(struct drm_plane *plane)
 {
        struct intel_plane_state *plane_state = to_intel_plane_state(plane->state);
+       struct intel_crtc_state *crtc_state = to_intel_crtc_state(plane->state->crtc->state);
        struct intel_plane *iplane = to_intel_plane(plane);
        struct intel_display *display = to_intel_display(iplane);
        struct drm_framebuffer *fb = plane_state->hw.fb;
@@ -1327,6 +1329,11 @@ static void intel_panic_flush(struct drm_plane *plane)
 
        intel_bo_panic_finish(intel_fb);
 
+       if (crtc_state->enable_psr2_sel_fetch) {
+               /* Force a full update for psr2 */
+               intel_psr2_panic_force_full_update(display, crtc_state);
+       }
+
        /* Flush the cache and don't disable tiling if it's the fbdev framebuffer.*/
        if (intel_fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) {
                struct iosys_map map;
index f7837e17c59dfa29514af3b4fb7988aaec73dfbf..8ee9d9dbdf11e64ddec33a561f19bb1397fd3e23 100644 (file)
@@ -2888,6 +2888,26 @@ skip_sel_fetch_set_loop:
        return 0;
 }
 
+void intel_psr2_panic_force_full_update(struct intel_display *display,
+                                       struct intel_crtc_state *crtc_state)
+{
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+       u32 val = man_trk_ctl_enable_bit_get(display);
+
+       /* SF partial frame enable has to be set even on full update */
+       val |= man_trk_ctl_partial_frame_bit_get(display);
+       val |= man_trk_ctl_continuos_full_frame(display);
+
+       /* Directly write the register */
+       intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val);
+
+       if (!crtc_state->enable_psr2_su_region_et)
+               return;
+
+       intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0);
+}
+
 void intel_psr_pre_plane_update(struct intel_atomic_state *state,
                                struct intel_crtc *crtc)
 {
index 0cf53184f13f9c84107915f2ab792bdb665d0311..9b061a22361f31a9fb4b871354bf778c6a39549e 100644 (file)
@@ -57,6 +57,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
                                struct intel_crtc *crtc);
 void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
                                          const struct intel_crtc_state *crtc_state);
+void intel_psr2_panic_force_full_update(struct intel_display *display,
+                                       struct intel_crtc_state *crtc_state);
 void intel_psr_pause(struct intel_dp *intel_dp);
 void intel_psr_resume(struct intel_dp *intel_dp);
 bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state);