{ HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) },
};
-struct hvf_sreg_match {
- int reg;
- uint32_t cp_idx;
-};
-
/*
* QEMU uses KVM system register ids in the migration format.
* Conveniently, HVF uses the same encoding of the op* and cr* parameters
#undef DEF_SYSREG
-#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) { HVF_ID },
+#define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) HVF_ID,
-static struct hvf_sreg_match hvf_sreg_match[] = {
+static const hv_sys_reg_t hvf_sreg_list[] = {
#include "sysreg.c.inc"
};
hv_return_t ret;
uint64_t val;
hv_simd_fp_uchar16_t fpval;
- int i;
+ int i, n;
for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
ret = hv_vcpu_get_reg(cpu->accel->fd, hvf_reg_match[i].reg, &val);
assert_hvf_ok(ret);
pstate_write(env, val);
- for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
- int hvf_id = hvf_sreg_match[i].reg;
- uint64_t kvm_id = HVF_TO_KVMID(hvf_id);
-
- if (hvf_sreg_match[i].cp_idx == -1) {
- continue;
- }
+ for (i = 0, n = arm_cpu->cpreg_array_len; i < n; i++) {
+ uint64_t kvm_id = arm_cpu->cpreg_indexes[i];
+ int hvf_id = KVMID_TO_HVF(kvm_id);
if (cpu->accel->guest_debug_enabled) {
/* Handle debug registers */
val = read_raw_cp_reg(env, ri);
- arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
+ arm_cpu->cpreg_values[i] = val;
continue;
}
}
ret = hv_vcpu_get_sys_reg(cpu->accel->fd, hvf_id, &val);
assert_hvf_ok(ret);
- arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
+ arm_cpu->cpreg_values[i] = val;
}
assert(write_list_to_cpustate(arm_cpu));
hv_return_t ret;
uint64_t val;
hv_simd_fp_uchar16_t fpval;
- int i;
+ int i, n;
for (i = 0; i < ARRAY_SIZE(hvf_reg_match); i++) {
val = *(uint64_t *)((void *)env + hvf_reg_match[i].offset);
aarch64_save_sp(env, arm_current_el(env));
assert(write_cpustate_to_list(arm_cpu, false));
- for (i = 0; i < ARRAY_SIZE(hvf_sreg_match); i++) {
- int hvf_id = hvf_sreg_match[i].reg;
-
- if (hvf_sreg_match[i].cp_idx == -1) {
- continue;
- }
+ for (i = 0, n = arm_cpu->cpreg_array_len; i < n; i++) {
+ uint64_t kvm_id = arm_cpu->cpreg_indexes[i];
+ int hvf_id = KVMID_TO_HVF(kvm_id);
if (cpu->accel->guest_debug_enabled) {
/* Handle debug registers */
}
}
- val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx];
+ val = arm_cpu->cpreg_values[i];
ret = hv_vcpu_set_sys_reg(cpu->accel->fd, hvf_id, val);
assert_hvf_ok(ret);
}
{
ARMCPU *arm_cpu = ARM_CPU(cpu);
CPUARMState *env = &arm_cpu->env;
- uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match);
+ uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_list);
uint32_t sregs_cnt = 0;
uint64_t pfr;
hv_return_t ret;
/* Populate cp list for all known sysregs */
for (i = 0; i < sregs_match_len; i++) {
- int hvf_id = hvf_sreg_match[i].reg;
+ hv_sys_reg_t hvf_id = hvf_sreg_list[i];
uint64_t kvm_id = HVF_TO_KVMID(hvf_id);
uint32_t key = kvm_to_cpreg_id(kvm_id);
const ARMCPRegInfo *ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
if (ri) {
assert(!(ri->type & ARM_CP_NO_RAW));
- hvf_sreg_match[i].cp_idx = sregs_cnt;
arm_cpu->cpreg_indexes[sregs_cnt++] = kvm_id;
- } else {
- hvf_sreg_match[i].cp_idx = -1;
}
}
arm_cpu->cpreg_array_len = sregs_cnt;