}
}
-static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
- int pps, u32 *pps_val)
+static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
+ bool *check_equal)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
i915_reg_t dsc_reg[2];
int i, vdsc_per_pipe, dsc_reg_num;
+ u32 val = 0;
vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
- *pps_val = 0;
+ if (check_equal)
+ *check_equal = true;
for (i = 0; i < dsc_reg_num; i++) {
- u32 pps_temp;
+ u32 tmp;
- pps_temp = intel_de_read(i915, dsc_reg[i]);
+ tmp = intel_de_read(i915, dsc_reg[i]);
- if (i == 0)
- *pps_val = pps_temp;
- else if (pps_temp != *pps_val)
- return false;
+ if (i == 0) {
+ val = tmp;
+ } else if (check_equal && tmp != val) {
+ *check_equal = false;
+ break;
+ } else if (!check_equal) {
+ break;
+ }
}
- return true;
+ return val;
}
static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
u32 val;
- int ret;
+ bool all_equal;
- ret = intel_dsc_read_pps_reg(crtc_state, pps, &val);
- drm_WARN_ON(&i915->drm, !ret);
+ val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
+ drm_WARN_ON(&i915->drm, !all_equal);
return val;
}