cxl/pci: Check Mem_info_valid bit for each applicable DVSEC

In theory a device might set the mem_info_valid bit for a first range
after it is ready but before as second range has reached that state.
Therefore, the correct approach is to check the Mem_info_valid bit for
each applicable DVSEC range against HDM_COUNT, rather than only for the
DVSEC range 1. Consequently, let's move the check into the "for loop"
that handles each DVSEC range.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Yanfei Xu <yanfei.xu@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240828084231.1378789-4-yanfei.xu@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 37e537e50b3467cd3fb419f35ec344baa0ad8b0c..043775f3f9a5b0e92fadf0a7a765b7982a696def 100644 (file)
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -324,10 +324,6 @@ int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,
        if (!hdm_count || hdm_count > 2)
                return -EINVAL;
 
-       rc = cxl_dvsec_mem_range_valid(cxlds, 0);
-       if (rc)
-               return rc;
-
        /*
         * The current DVSEC values are moot if the memory capability is
         * disabled, and they will remain moot after the HDM Decoder
@@ -345,6 +341,10 @@ int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port,
                u64 base, size;
                u32 temp;
 
+               rc = cxl_dvsec_mem_range_valid(cxlds, i);
+               if (rc)
+                       return rc;
+
                rc = pci_read_config_dword(
                        pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp);
                if (rc)