RISC-V: Add test for vec_duplicate + vsaddu.vv combine case 0 with GR2VR cost 0,...

Add asm dump check and run test for vec_duplicate + vsaddu.vv
combine to vsaddu.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
	helper macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index bcfd5145d24f6a85448d8eb54b979345d85e5433..21a207edce753ccf94b8ac493163579bfcb5116c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vremu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index b9a6a28309162e1d440efd849b68096be59b3ac7..d1063adb0d6cde1f06c6c5ecf45d56ccaac46f96 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vremu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index abb5e5e7842893699ac5426c9dbf54370ad129da..3d96503fd9adc9f4879c8260614b4974c6e8a8ac 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vremu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 50065d0973b276a062729ba11a1c51e5954ebace..339a35c3f422869a797d25be35aaea077d414a85 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vremu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */
+/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index c03560a810f4b3f86c77f8e0c637f01da193e71a..bc3c53f520c25b59de1a083f831c85ddd54fec95 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vremu.vx} } } */
 /* { dg-final { scan-assembler-not {vmaxu.vx} } } */
 /* { dg-final { scan-assembler-not {vminu.vx} } } */
+/* { dg-final { scan-assembler-not {vsaddu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 70fc262f3f513b5f5507296b93fd0bc96a37e46d..014b614a693a4ac3cc7b17df4adc9ac734d2e368 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vremu.vx} } } */
 /* { dg-final { scan-assembler-not {vmaxu.vx} } } */
 /* { dg-final { scan-assembler-not {vminu.vx} } } */
+/* { dg-final { scan-assembler-not {vsaddu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index a368c9680d4845213b27bebb6c13ed12f7d1ef83..9cb3571c0880ff564057a620dd5fa85df8ec51e3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vremu.vx} } } */
 /* { dg-final { scan-assembler-not {vmaxu.vx} } } */
 /* { dg-final { scan-assembler-not {vminu.vx} } } */
+/* { dg-final { scan-assembler-not {vsaddu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index 581da35084138ebe0d7e5521b35128d0645d9a28..981e55fdf5942edef29edc3a7f100c9aff6624c6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vremu.vx} } } */
 /* { dg-final { scan-assembler-not {vmaxu.vx} } } */
 /* { dg-final { scan-assembler-not {vminu.vx} } } */
+/* { dg-final { scan-assembler-not {vsaddu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 0620953c3bb9aa76686273d691a27d49aa4d13b5..82ace5ad51c05a2e24b02058bc3a2461d0a691f0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vremu.vx} } } */
 /* { dg-final { scan-assembler-not {vmaxu.vx} } } */
 /* { dg-final { scan-assembler-not {vminu.vx} } } */
+/* { dg-final { scan-assembler-not {vsaddu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 0aca5b90b4abde5defe24e5e9d9a5e4db8077f34..4f57f8577a0296c73bc1925d075c10f160b8e5a6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vremu.vx} } } */
 /* { dg-final { scan-assembler-not {vmaxu.vx} } } */
 /* { dg-final { scan-assembler-not {vminu.vx} } } */
+/* { dg-final { scan-assembler-not {vsaddu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 4dd8f1a0a29d9160d37465d771c67cc1856aca93..80ad3359478461f7744a20c71e9fbcce19354646 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vremu.vx} } } */
 /* { dg-final { scan-assembler-not {vmaxu.vx} } } */
 /* { dg-final { scan-assembler-not {vminu.vx} } } */
+/* { dg-final { scan-assembler-not {vsaddu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index 1508ff3b3b6b18dc4f4acc640edf8108fcce7f1a..a4080ff640f71be798617e5a4984a108ea14661f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -17,3 +17,4 @@ TEST_BINARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vremu.vx} } } */
 /* { dg-final { scan-assembler-not {vmaxu.vx} } } */
 /* { dg-final { scan-assembler-not {vminu.vx} } } */
+/* { dg-final { scan-assembler-not {vsaddu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index f47586b39be2188b82625453fb0227215bcc7fab..2932e189186074524ab5469beb0ffbfa76f9b2d8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -270,6 +270,21 @@ test_vx_binary_##NAME##_##FUNC##_##T##_case_3 (T * restrict out, \
   VX_BINARY_FUNC_BODY_X64(op)        \
   VX_BINARY_FUNC_BODY_X64(op)
 
+#define DEF_SAT_U_ADD(T)                   \
+T                                          \
+test_##T##_sat_add (T a, T b)              \
+{                                          \
+  return (a + b) | (-(T)((T)(a + b) < a)); \
+}
+
+DEF_SAT_U_ADD(uint8_t)
+DEF_SAT_U_ADD(uint16_t)
+DEF_SAT_U_ADD(uint32_t)
+DEF_SAT_U_ADD(uint64_t)
+
+#define SAT_U_ADD_FUNC(T) test_##T##_sat_add
+#define SAT_U_ADD_FUNC_WRAP(T) SAT_U_ADD_FUNC(T)
+
 #define TEST_BINARY_VX_SIGNED_0(T)                      \
   DEF_VX_BINARY_CASE_0_WRAP(T, +, add)                  \
   DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)                  \
@@ -285,18 +300,19 @@ test_vx_binary_##NAME##_##FUNC##_##T##_case_3 (T * restrict out, \
   DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \
   DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_1_WARP(T), min)
 
-#define TEST_BINARY_VX_UNSIGNED_0(T)                    \
-  DEF_VX_BINARY_CASE_0_WRAP(T, +, add)                  \
-  DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)                  \
-  DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)         \
-  DEF_VX_BINARY_CASE_0_WRAP(T, &, and)                  \
-  DEF_VX_BINARY_CASE_0_WRAP(T, |, or)                   \
-  DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)                  \
-  DEF_VX_BINARY_CASE_0_WRAP(T, /, div)                  \
-  DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)                  \
-  DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \
-  DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \
-  DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \
-  DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_1_WARP(T), min)
+#define TEST_BINARY_VX_UNSIGNED_0(T)                       \
+  DEF_VX_BINARY_CASE_0_WRAP(T, +, add)                     \
+  DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)                     \
+  DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)            \
+  DEF_VX_BINARY_CASE_0_WRAP(T, &, and)                     \
+  DEF_VX_BINARY_CASE_0_WRAP(T, |, or)                      \
+  DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)                     \
+  DEF_VX_BINARY_CASE_0_WRAP(T, /, div)                     \
+  DEF_VX_BINARY_CASE_0_WRAP(T, %, rem)                     \
+  DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max)    \
+  DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max)    \
+  DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min)    \
+  DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_1_WARP(T), min)    \
+  DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_ADD_FUNC(T), sat_add)
 
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 96663016f0e035a12141584a85b4a7a430ac6c47..56c3d260e347e9491f82f33aadfedbb871a9be20 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -4122,4 +4122,200 @@ uint64_t TEST_BINARY_DATA(uint64_t, min)[][3][N] =
   },
 };
 
+uint8_t TEST_BINARY_DATA(uint8_t, sat_add)[][3][N] =
+{
+  {
+    { 0 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+  },
+  {
+    { 127 },
+    {
+       127,  127,  127,  127,
+       128,  128,  128,  128,
+       255,  255,  255,  255,
+         1,    1,    1,    1,
+    },
+    {
+       254,  254,  254,  254,
+       255,  255,  255,  255,
+       255,  255,  255,  255,
+       128,  128,  128,  128,
+    },
+  },
+  {
+    { 254 },
+    {
+       128,  128,  128,  128,
+       255,  255,  255,  255,
+       127,  127,  127,  127,
+         2,    2,    2,    2,
+    },
+    {
+       255,  255,  255,  255,
+       255,  255,  255,  255,
+       255,  255,  255,  255,
+       255,  255,  255,  255,
+    },
+  },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, sat_add)[][3][N] =
+{
+  {
+    { 0 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+  },
+  {
+    { 32767 },
+    {
+       32767,  32767,  32767,  32767,
+       32768,  32768,  32768,  32768,
+       65535,  65535,  65535,  65535,
+           1,      1,      1,      1,
+    },
+    {
+       65534,  65534,  65534,  65534,
+       65535,  65535,  65535,  65535,
+       65535,  65535,  65535,  65535,
+       32768,  32768,  32768,  32768,
+    },
+  },
+  {
+    { 65534 },
+    {
+       32768,  32768,  32768,  32768,
+       65535,  65535,  65535,  65535,
+       32767,  32767,  32767,  32767,
+           2,      2,      2,      2,
+    },
+    {
+       65535,  65535,  65535,  65535,
+       65535,  65535,  65535,  65535,
+       65535,  65535,  65535,  65535,
+       65535,  65535,  65535,  65535,
+    },
+  },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, sat_add)[][3][N] =
+{
+  {
+    { 0 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+  },
+  {
+    { 2147483647 },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+       2147483648,  2147483648,  2147483648,  2147483648,
+       4294967295,  4294967295,  4294967295,  4294967295,
+                1,           1,           1,           1,
+    },
+    {
+       4294967294,  4294967294,  4294967294,  4294967294,
+       4294967295,  4294967295,  4294967295,  4294967295,
+       4294967295,  4294967295,  4294967295,  4294967295,
+       2147483648,  2147483648,  2147483648,  2147483648,
+    },
+  },
+  {
+    { 4294967294 },
+    {
+       2147483648,  2147483648,  2147483648,  2147483648,
+       4294967295,  4294967295,  4294967295,  4294967295,
+       2147483647,  2147483647,  2147483647,  2147483647,
+                2,           2,           2,           2,
+    },
+    {
+       4294967295,  4294967295,  4294967295,  4294967295,
+       4294967295,  4294967295,  4294967295,  4294967295,
+       4294967295,  4294967295,  4294967295,  4294967295,
+       4294967295,  4294967295,  4294967295,  4294967295,
+    },
+  },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, sat_add)[][3][N] =
+{
+  {
+    { 0 },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+    {
+       2,  2,  2,  2,
+       1,  1,  1,  1,
+       0,  0,  0,  0,
+       4,  4,  4,  4,
+    },
+  },
+  {
+    { 9223372036854775807ull },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+       9223372036854775808ull,  9223372036854775808ull,  9223372036854775808ull,  9223372036854775808ull,
+      18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull,
+                            1,                       1,                       1,                       1,
+    },
+    {
+       18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,  18446744073709551614ull,
+       18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,
+       18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,
+        9223372036854775808ull,   9223372036854775808ull,   9223372036854775808ull,   9223372036854775808ull,
+    },
+  },
+  {
+    { 18446744073709551614ull },
+    {
+       9223372036854775808ull,  9223372036854775808ull,  9223372036854775808ull,  9223372036854775808ull,
+      18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull,
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+                            2,                       2,                       2,                       2,
+    },
+    {
+       18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,
+       18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,
+       18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,
+       18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,  18446744073709551615ull,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c
new file mode 100644 (file)
index 0000000..e1531b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T          uint16_t
+#define NAME       sat_add
+#define FUNC       SAT_U_ADD_FUNC_WRAP(T)
+#define TEST_DATA  TEST_BINARY_DATA_WRAP(T, NAME)
+
+DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME)
+
+#define TEST_RUN(T, NAME, out, in, x, n) \
+  RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c
new file mode 100644 (file)
index 0000000..4aa7143
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T          uint32_t
+#define NAME       sat_add
+#define FUNC       SAT_U_ADD_FUNC_WRAP(T)
+#define TEST_DATA  TEST_BINARY_DATA_WRAP(T, NAME)
+
+DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME)
+
+#define TEST_RUN(T, NAME, out, in, x, n) \
+  RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c
new file mode 100644 (file)
index 0000000..30992c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T          uint64_t
+#define NAME       sat_add
+#define FUNC       SAT_U_ADD_FUNC_WRAP(T)
+#define TEST_DATA  TEST_BINARY_DATA_WRAP(T, NAME)
+
+DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME)
+
+#define TEST_RUN(T, NAME, out, in, x, n) \
+  RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c
new file mode 100644 (file)
index 0000000..c6852a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c
@@ -0,0 +1,17 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T          uint8_t
+#define NAME       sat_add
+#define FUNC       SAT_U_ADD_FUNC_WRAP(T)
+#define TEST_DATA  TEST_BINARY_DATA_WRAP(T, NAME)
+
+DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME)
+
+#define TEST_RUN(T, NAME, out, in, x, n) \
+  RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n)
+
+#include "vx_binary_run.h"