]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/i915/bw: pass struct dram_info pointer around
authorJani Nikula <jani.nikula@intel.com>
Tue, 27 May 2025 09:25:21 +0000 (12:25 +0300)
committerJani Nikula <jani.nikula@intel.com>
Wed, 4 Jun 2025 15:57:22 +0000 (18:57 +0300)
Have just one place to figure out the pointer to struct dram_info, and
pass that around. This simplifies future changes.

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Link: https://lore.kernel.org/r/1752b4987ff39a685c28cebae1be4ce326b67c7b.1748337870.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_bw.c

index a5dd2932b852d656a70794e91f1eb0dec5ec98e6..6c537635b120c6aa1ace82ca69108e80fba2efa0 100644 (file)
@@ -218,11 +218,10 @@ intel_read_qgv_point_info(struct intel_display *display,
 }
 
 static int icl_get_qgv_points(struct intel_display *display,
+                             const struct dram_info *dram_info,
                              struct intel_qgv_info *qi,
                              bool is_y_tile)
 {
-       struct drm_i915_private *i915 = to_i915(display->drm);
-       const struct dram_info *dram_info = &i915->dram_info;
        int i, ret;
 
        qi->num_points = dram_info->num_qgv_points;
@@ -418,19 +417,20 @@ static const struct intel_sa_info xe3lpd_sa_info = {
        .derating = 10,
 };
 
-static int icl_get_bw_info(struct intel_display *display, const struct intel_sa_info *sa)
+static int icl_get_bw_info(struct intel_display *display,
+                          const struct dram_info *dram_info,
+                          const struct intel_sa_info *sa)
 {
-       struct drm_i915_private *i915 = to_i915(display->drm);
        struct intel_qgv_info qi = {};
        bool is_y_tile = true; /* assume y tile may be used */
-       int num_channels = max_t(u8, 1, i915->dram_info.num_channels);
+       int num_channels = max_t(u8, 1, dram_info->num_channels);
        int ipqdepth, ipqdepthpch = 16;
        int dclk_max;
        int maxdebw;
        int num_groups = ARRAY_SIZE(display->bw.max);
        int i, ret;
 
-       ret = icl_get_qgv_points(display, &qi, is_y_tile);
+       ret = icl_get_qgv_points(display, dram_info, &qi, is_y_tile);
        if (ret) {
                drm_dbg_kms(display->drm,
                            "Failed to get memory subsystem information, ignoring bandwidth limits");
@@ -488,11 +488,11 @@ static int icl_get_bw_info(struct intel_display *display, const struct intel_sa_
        return 0;
 }
 
-static int tgl_get_bw_info(struct intel_display *display, const struct intel_sa_info *sa)
+static int tgl_get_bw_info(struct intel_display *display,
+                          const struct dram_info *dram_info,
+                          const struct intel_sa_info *sa)
 {
-       struct drm_i915_private *i915 = to_i915(display->drm);
        struct intel_qgv_info qi = {};
-       const struct dram_info *dram_info = &i915->dram_info;
        bool is_y_tile = true; /* assume y tile may be used */
        int num_channels = max_t(u8, 1, dram_info->num_channels);
        int ipqdepth, ipqdepthpch = 16;
@@ -502,7 +502,7 @@ static int tgl_get_bw_info(struct intel_display *display, const struct intel_sa_
        int num_groups = ARRAY_SIZE(display->bw.max);
        int i, ret;
 
-       ret = icl_get_qgv_points(display, &qi, is_y_tile);
+       ret = icl_get_qgv_points(display, dram_info, &qi, is_y_tile);
        if (ret) {
                drm_dbg_kms(display->drm,
                            "Failed to get memory subsystem information, ignoring bandwidth limits");
@@ -632,15 +632,15 @@ static void dg2_get_bw_info(struct intel_display *display)
 }
 
 static int xe2_hpd_get_bw_info(struct intel_display *display,
+                              const struct dram_info *dram_info,
                               const struct intel_sa_info *sa)
 {
-       struct drm_i915_private *i915 = to_i915(display->drm);
        struct intel_qgv_info qi = {};
-       int num_channels = i915->dram_info.num_channels;
+       int num_channels = dram_info->num_channels;
        int peakbw, maxdebw;
        int ret, i;
 
-       ret = icl_get_qgv_points(display, &qi, true);
+       ret = icl_get_qgv_points(display, dram_info, &qi, true);
        if (ret) {
                drm_dbg_kms(display->drm,
                            "Failed to get memory subsystem information, ignoring bandwidth limits");
@@ -769,26 +769,26 @@ void intel_bw_init_hw(struct intel_display *display)
                return;
 
        if (DISPLAY_VER(display) >= 30)
-               tgl_get_bw_info(display, &xe3lpd_sa_info);
+               tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
        else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx &&
                 dram_info->type == INTEL_DRAM_GDDR_ECC)
-               xe2_hpd_get_bw_info(display, &xe2_hpd_ecc_sa_info);
+               xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
        else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)
-               xe2_hpd_get_bw_info(display, &xe2_hpd_sa_info);
+               xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
        else if (DISPLAY_VER(display) >= 14)
-               tgl_get_bw_info(display, &mtl_sa_info);
+               tgl_get_bw_info(display, dram_info, &mtl_sa_info);
        else if (display->platform.dg2)
                dg2_get_bw_info(display);
        else if (display->platform.alderlake_p)
-               tgl_get_bw_info(display, &adlp_sa_info);
+               tgl_get_bw_info(display, dram_info, &adlp_sa_info);
        else if (display->platform.alderlake_s)
-               tgl_get_bw_info(display, &adls_sa_info);
+               tgl_get_bw_info(display, dram_info, &adls_sa_info);
        else if (display->platform.rocketlake)
-               tgl_get_bw_info(display, &rkl_sa_info);
+               tgl_get_bw_info(display, dram_info, &rkl_sa_info);
        else if (DISPLAY_VER(display) == 12)
-               tgl_get_bw_info(display, &tgl_sa_info);
+               tgl_get_bw_info(display, dram_info, &tgl_sa_info);
        else if (DISPLAY_VER(display) == 11)
-               icl_get_bw_info(display, &icl_sa_info);
+               icl_get_bw_info(display, dram_info, &icl_sa_info);
 }
 
 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)