Daily bump.

diff --git a/contrib/ChangeLog b/contrib/ChangeLog
index 3b639f40d7d719a459ca5b7151f5f0209d22f58e..9c1dd3a17f48864440b03bca7e3e1b73a6821711 100644 (file)
--- a/contrib/ChangeLog
+++ b/contrib/ChangeLog
@@ -1,3 +1,7 @@
+2022-12-28  Martin Liska  <mliska@suse.cz>
+
+       * update-copyright.py: Add contrib folder.
+
 2022-12-23  Arsen Arsenović  <arsen@aarsen.me>
 
        * dg-out-generator.pl: New file.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f670edf4ae81befbca625121273da28eba7fba63..b43b03d06c4f2b76cd65f45c4baf5ae0bd72a738 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,36 @@
+2022-12-28  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * config/i386/i386.md (*clzsi2_lzcnt_zext_2): define_insn_and_split
+       to match ZERO_EXTEND form of *clzsi2_lzcnt_zext.
+       (*clzsi2_lzcnt_zext_2_falsedep): Likewise, new define_insn to match
+       ZERO_EXTEND form of *clzsi2_lzcnt_zext_falsedep.
+       (*bmi2_bzhi_zero_extendsidi_5): Likewise, new define_insn to match
+       ZERO_EXTEND form of *bmi2_bzhi_zero_extendsidi.
+       (*popcountsi2_zext_2): Likewise, new define_insn_and_split to match
+       ZERO_EXTEND form of *popcountsi2_zext.
+       (*popcountsi2_zext_2_falsedep): Likewise, new define_insn to match
+       ZERO_EXTEND form of *popcountsi2_zext_falsedep.
+       (*popcounthi2_2): Likewise, new define_insn_and_split to match
+       ZERO_EXTEND form of *popcounthi2.
+       (define_peephole2): ZERO_EXTEND variant of HImode popcount&1 using
+       parity flag peephole2.
+
+2022-12-28  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * config/i386/i386-expand.cc (ix86_split_ashl): Call
+       ix86_expand_clear to generate an xor instruction.
+
+2022-12-28  Martin Liska  <mliska@suse.cz>
+
+       PR tree-optimization/108137
+       * tree-ssa-strlen.cc (get_range_strlen_phi): Reject anything
+       different from INTEGER_CST.
+
+2022-12-28  Kito Cheng  <kito.cheng@sifive.com>
+
+       * config/riscv/riscv-vsetvl.h (vl_vtype_info::get_avl_info):
+       Return const reference rather than value.
+
 2022-12-27  Jeff Law  <jlaw@ventanamicro.com>
 
        * config/riscv/riscv.md: Add missing modes to last patch.t

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e65d79fa1d571a9399640c78dc90cd38b6a3cca0..cf083afb2477966822744b4ddda5647d304ebf40 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20221228
+20221229

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7dd0a49240228ee84bb6a4914b0487c39a769aa0..da85e7935b9e5a1f22c35824acb32213fd4368d0 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2022-12-28  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * gcc.target/i386/ashlti3-1.c: New test case.
+
+2022-12-28  Martin Liska  <mliska@suse.cz>
+
+       PR tree-optimization/108137
+       * gcc.dg/tree-ssa/pr108137.c: New test.
+
 2022-12-27  Raphael Moreira Zinsly  <rzinsly@ventanamicro.com>
 
        PR target/95632