phy: mediatek: tphy: add support force phy mode switch

this is used to be compatible with old SoCs, such as mt8195, which shares
t-phy between usb3 and pcie controller, usually, it's default mode is pcie
rc mode, and could use force mode to switch into usb3 mode, because pericfg
layer doesn't provide mode switch, also no efuse or jumper can be used;
Currently, only support switch from default pcie mode to usb3;
Note: don't use this way on new SoCs, use pericfg layer's mode switch
instead (by perperty "mediatek,syscon-type").

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20231211025624.28991-2-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 05eab9014132fc9ff782e855e2c2351e8cedb64d..a4746f6cb8a187e2a1172fd5fc2dd1f7ceee7bb1 100644 (file)
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -185,6 +185,10 @@
 #define P3D_RG_CDR_BIR_LTD1            GENMASK(28, 24)
 #define P3D_RG_CDR_BIR_LTD0            GENMASK(12, 8)
 
+#define U3P_U3_PHYD_TOP1               0x100
+#define P3D_RG_PHY_MODE                        GENMASK(2, 1)
+#define P3D_RG_FORCE_PHY_MODE          BIT(0)
+
 #define U3P_U3_PHYD_RXDET1             0x128
 #define P3D_RG_RXDET_STB2_SET          GENMASK(17, 9)
 
@@ -327,6 +331,7 @@ struct mtk_phy_instance {
        int discth;
        int pre_emphasis;
        bool bc12_en;
+       bool type_force_mode;
 };
 
 struct mtk_tphy {
@@ -768,6 +773,23 @@ static void u3_phy_instance_init(struct mtk_tphy *tphy,
        void __iomem *phya = u3_banks->phya;
        void __iomem *phyd = u3_banks->phyd;
 
+       if (instance->type_force_mode) {
+               /* force phy as usb mode, default is pcie rc mode */
+               mtk_phy_update_field(phyd + U3P_U3_PHYD_TOP1, P3D_RG_PHY_MODE, 1);
+               mtk_phy_set_bits(phyd + U3P_U3_PHYD_TOP1, P3D_RG_FORCE_PHY_MODE);
+               /* power down phy by ip and pipe reset */
+               mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,
+                                P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN);
+               mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,
+                                P3C_RG_SWRST_U3_PHYD | P3C_RG_SWRST_U3_PHYD_FORCE_EN);
+               udelay(10);
+               /* power on phy again */
+               mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD,
+                                  P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN);
+               mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE,
+                                  P3C_RG_SWRST_U3_PHYD | P3C_RG_SWRST_U3_PHYD_FORCE_EN);
+       }
+
        /* gating PCIe Analog XTAL clock */
        mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
                         XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
@@ -1120,6 +1142,9 @@ static void phy_parse_property(struct mtk_tphy *tphy,
 {
        struct device *dev = &instance->phy->dev;
 
+       if (instance->type == PHY_TYPE_USB3)
+               instance->type_force_mode = device_property_read_bool(dev, "mediatek,force-mode");
+
        if (instance->type != PHY_TYPE_USB2)
                return;