Merge branch kvm-arm64/idregs-6.12 into kvmarm/fixes

* kvm-arm64/idregs-6.12:
  : .
  : Make some fields of ID_AA64DFR0_EL1 and ID_AA64PFR1_EL1
  : writable from userspace, so that a VMM can influence the
  : set of guest-visible features.
  :
  : - for ID_AA64DFR0_EL1: DoubleLock, WRPs, PMUVer and DebugVer
  :   are writable (courtesy of Shameer Kolothum)
  :
  : - for ID_AA64PFR1_EL1: BT, SSBS, CVS2_frac are writable
  :   (courtesy of Shaoqin Huang)
  : .
  KVM: selftests: aarch64: Add writable test for ID_AA64PFR1_EL1
  KVM: arm64: Allow userspace to change ID_AA64PFR1_EL1
  KVM: arm64: Use kvm_has_feat() to check if FEAT_SSBS is advertised to the guest
  KVM: arm64: Disable fields that KVM doesn't know how to handle in ID_AA64PFR1_EL1
  KVM: arm64: Make the exposed feature bits in AA64DFR0_EL1 writable from userspace

Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --cc arch/arm64/kvm/sys_regs.c
index dad88e31f9537fe02e28b117d6a740f15572e0ba,da7b8e078b209d3848aa7d65ae48d9b1ea52d2f7..c75dfc702a5c822410869cd4980eec6de7293d0e
--- 1/arch/arm64/kvm/sys_regs.c
--- 2/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@@ -1527,11 -1538,15 +1527,19 @@@ static u64 __kvm_read_sanitised_id_reg(
                        val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
  
                val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
+               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap);
+               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI);
+               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac);
+               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS);
+               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE);
+               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX);
+               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2);
+               val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR);
                break;
 +      case SYS_ID_AA64PFR2_EL1:
 +              /* We only expose FPMR */
 +              val &= ID_AA64PFR2_EL1_FPMR;
 +              break;
        case SYS_ID_AA64ISAR1_EL1:
                if (!vcpu_has_ptrauth(vcpu))
                        val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
@@@ -2374,10 -2367,23 +2382,22 @@@ static const struct sys_reg_desc sys_re
                   ID_AA64PFR0_EL1_MPAM |
                   ID_AA64PFR0_EL1_SVE |
                   ID_AA64PFR0_EL1_RAS |
 -                 ID_AA64PFR0_EL1_GIC |
                   ID_AA64PFR0_EL1_AdvSIMD |
                   ID_AA64PFR0_EL1_FP), },
-       ID_SANITISED(ID_AA64PFR1_EL1),
+       ID_WRITABLE(ID_AA64PFR1_EL1, ~(ID_AA64PFR1_EL1_PFAR |
+                                      ID_AA64PFR1_EL1_DF2 |
+                                      ID_AA64PFR1_EL1_MTEX |
+                                      ID_AA64PFR1_EL1_THE |
+                                      ID_AA64PFR1_EL1_GCS |
+                                      ID_AA64PFR1_EL1_MTE_frac |
+                                      ID_AA64PFR1_EL1_NMI |
+                                      ID_AA64PFR1_EL1_RNDR_trap |
+                                      ID_AA64PFR1_EL1_SME |
+                                      ID_AA64PFR1_EL1_RES0 |
+                                      ID_AA64PFR1_EL1_MPAM_frac |
+                                      ID_AA64PFR1_EL1_RAS_frac |
+                                      ID_AA64PFR1_EL1_MTE)),
 -      ID_UNALLOCATED(4,2),
 +      ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR),
        ID_UNALLOCATED(4,3),
        ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0),
        ID_HIDDEN(ID_AA64SMFR0_EL1),

diff --cc tools/testing/selftests/kvm/aarch64/set_id_regs.c
Simple merge