This testcase FAIL in RISC-V because RISC-V support vect_load_lanes with 6.
FAIL: gcc.dg/vect/slp-16.c -flto -ffat-lto-objects scan-tree-dump-times vect "vectorizing stmts using SLP" 2
FAIL: gcc.dg/vect/slp-16.c scan-tree-dump-times vect "vectorizing stmts using SLP" 2
Since it use vlseg6 (vect_load_lanes with array size = 6)
gcc/testsuite/ChangeLog:
* gcc.dg/vect/slp-16.c: Block vect_strided6.
* lib/target-supports.exp: Add strided type.
}
/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_int_mult } } } */
-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target vect_int_mult } } } */
+/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" { target { vect_int_mult && {! vect_strided6 } } } } } */
&& [check_effective_target_s390_vx]) }}]
}
-foreach N {2 3 4 8} {
+foreach N {2 3 4 5 6 7 8} {
eval [string map [list N $N] {
# Return 1 if the target supports 2-vector interleaving
proc check_effective_target_vect_stridedN { } {