perf/x86/intel/uncore: Add Lunar Lake support

The uncore subsystem for Lunar Lake is similar to the previous
Meteor Lake. The uncore PerfMon registers are located at both
MSR and MMIO space.

The ARB and iMC are kept. There is no difference from the Meteor Lake.
Move the global control initialization to the first box of the CBOX.

The sNCU is moved to the MMIO space.

The HBO is newly added and only be accessed from the MMIO space.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20240731141353.759643-3-kan.liang@linux.intel.com

diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index 42968ad5101b2e806bc46aa56e587262352be97a..d98fac56768469e051ee0be3932d4dbf01e34a3d 100644 (file)
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -1816,6 +1816,11 @@ static const struct intel_uncore_init_fun mtl_uncore_init __initconst = {
        .mmio_init = adl_uncore_mmio_init,
 };
 
+static const struct intel_uncore_init_fun lnl_uncore_init __initconst = {
+       .cpu_init = lnl_uncore_cpu_init,
+       .mmio_init = lnl_uncore_mmio_init,
+};
+
 static const struct intel_uncore_init_fun icx_uncore_init __initconst = {
        .cpu_init = icx_uncore_cpu_init,
        .pci_init = icx_uncore_pci_init,
@@ -1896,6 +1901,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = {
        X86_MATCH_VFM(INTEL_ARROWLAKE,          &mtl_uncore_init),
        X86_MATCH_VFM(INTEL_ARROWLAKE_U,        &mtl_uncore_init),
        X86_MATCH_VFM(INTEL_ARROWLAKE_H,        &mtl_uncore_init),
+       X86_MATCH_VFM(INTEL_LUNARLAKE_M,        &lnl_uncore_init),
        X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X,   &spr_uncore_init),
        X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X,    &spr_uncore_init),
        X86_MATCH_VFM(INTEL_GRANITERAPIDS_X,    &gnr_uncore_init),

diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
index 027ef292c60223119071fd5ebd1a253a96058fd0..79ff32e13dcc8127603c9bfac99e318d6ca24054 100644 (file)
--- a/arch/x86/events/intel/uncore.h
+++ b/arch/x86/events/intel/uncore.h
@@ -611,10 +611,12 @@ void skl_uncore_cpu_init(void);
 void icl_uncore_cpu_init(void);
 void tgl_uncore_cpu_init(void);
 void adl_uncore_cpu_init(void);
+void lnl_uncore_cpu_init(void);
 void mtl_uncore_cpu_init(void);
 void tgl_uncore_mmio_init(void);
 void tgl_l_uncore_mmio_init(void);
 void adl_uncore_mmio_init(void);
+void lnl_uncore_mmio_init(void);
 int snb_pci2phy_map_init(int devid);
 
 /* uncore_snbep.c */

diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
index 05fe6e90bd8eb5ffd60b3fc312560f851766f8c0..983beede73acae64de9e014060d7b2e0faa68daa 100644 (file)
--- a/arch/x86/events/intel/uncore_snb.c
+++ b/arch/x86/events/intel/uncore_snb.c
@@ -252,6 +252,7 @@ DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
 DEFINE_UNCORE_FORMAT_ATTR(threshold, threshold, "config:24-29");
+DEFINE_UNCORE_FORMAT_ATTR(threshold2, threshold, "config:24-31");
 
 /* Sandy Bridge uncore support */
 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
@@ -746,6 +747,34 @@ void mtl_uncore_cpu_init(void)
        uncore_msr_uncores = mtl_msr_uncores;
 }
 
+static struct intel_uncore_type *lnl_msr_uncores[] = {
+       &mtl_uncore_cbox,
+       &mtl_uncore_arb,
+       NULL
+};
+
+#define LNL_UNC_MSR_GLOBAL_CTL                 0x240e
+
+static void lnl_uncore_msr_init_box(struct intel_uncore_box *box)
+{
+       if (box->pmu->pmu_idx == 0)
+               wrmsrl(LNL_UNC_MSR_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
+}
+
+static struct intel_uncore_ops lnl_uncore_msr_ops = {
+       .init_box       = lnl_uncore_msr_init_box,
+       .disable_event  = snb_uncore_msr_disable_event,
+       .enable_event   = snb_uncore_msr_enable_event,
+       .read_counter   = uncore_msr_read_counter,
+};
+
+void lnl_uncore_cpu_init(void)
+{
+       mtl_uncore_cbox.num_boxes = 4;
+       mtl_uncore_cbox.ops = &lnl_uncore_msr_ops;
+       uncore_msr_uncores = lnl_msr_uncores;
+}
+
 enum {
        SNB_PCI_UNCORE_IMC,
 };
@@ -1716,3 +1745,107 @@ void adl_uncore_mmio_init(void)
 }
 
 /* end of Alder Lake MMIO uncore support */
+
+/* Lunar Lake MMIO uncore support */
+#define LNL_UNCORE_PCI_SAFBAR_OFFSET           0x68
+#define LNL_UNCORE_MAP_SIZE                    0x1000
+#define LNL_UNCORE_SNCU_BASE                   0xE4B000
+#define LNL_UNCORE_SNCU_CTR                    0x390
+#define LNL_UNCORE_SNCU_CTRL                   0x398
+#define LNL_UNCORE_SNCU_BOX_CTL                        0x380
+#define LNL_UNCORE_GLOBAL_CTL                  0x700
+#define LNL_UNCORE_HBO_BASE                    0xE54000
+#define LNL_UNCORE_HBO_OFFSET                  -4096
+#define LNL_UNCORE_HBO_CTR                     0x570
+#define LNL_UNCORE_HBO_CTRL                    0x550
+#define LNL_UNCORE_HBO_BOX_CTL                 0x548
+
+#define LNL_UNC_CTL_THRESHOLD                  0xff000000
+#define LNL_UNC_RAW_EVENT_MASK                 (SNB_UNC_CTL_EV_SEL_MASK | \
+                                                SNB_UNC_CTL_UMASK_MASK | \
+                                                SNB_UNC_CTL_EDGE_DET | \
+                                                SNB_UNC_CTL_INVERT | \
+                                                LNL_UNC_CTL_THRESHOLD)
+
+static struct attribute *lnl_uncore_formats_attr[] = {
+       &format_attr_event.attr,
+       &format_attr_umask.attr,
+       &format_attr_edge.attr,
+       &format_attr_inv.attr,
+       &format_attr_threshold2.attr,
+       NULL
+};
+
+static const struct attribute_group lnl_uncore_format_group = {
+       .name           = "format",
+       .attrs          = lnl_uncore_formats_attr,
+};
+
+static void lnl_uncore_hbo_init_box(struct intel_uncore_box *box)
+{
+       uncore_get_box_mmio_addr(box, LNL_UNCORE_HBO_BASE,
+                                LNL_UNCORE_PCI_SAFBAR_OFFSET,
+                                LNL_UNCORE_HBO_OFFSET);
+}
+
+static struct intel_uncore_ops lnl_uncore_hbo_ops = {
+       .init_box       = lnl_uncore_hbo_init_box,
+       MMIO_UNCORE_COMMON_OPS()
+};
+
+static struct intel_uncore_type lnl_uncore_hbo = {
+       .name           = "hbo",
+       .num_counters   = 4,
+       .num_boxes      = 2,
+       .perf_ctr_bits  = 64,
+       .perf_ctr       = LNL_UNCORE_HBO_CTR,
+       .event_ctl      = LNL_UNCORE_HBO_CTRL,
+       .event_mask     = LNL_UNC_RAW_EVENT_MASK,
+       .box_ctl        = LNL_UNCORE_HBO_BOX_CTL,
+       .mmio_map_size  = LNL_UNCORE_MAP_SIZE,
+       .ops            = &lnl_uncore_hbo_ops,
+       .format_group   = &lnl_uncore_format_group,
+};
+
+static void lnl_uncore_sncu_init_box(struct intel_uncore_box *box)
+{
+       uncore_get_box_mmio_addr(box, LNL_UNCORE_SNCU_BASE,
+                                LNL_UNCORE_PCI_SAFBAR_OFFSET,
+                                0);
+
+       if (box->io_addr)
+               writel(ADL_UNCORE_IMC_CTL_INT, box->io_addr + LNL_UNCORE_GLOBAL_CTL);
+}
+
+static struct intel_uncore_ops lnl_uncore_sncu_ops = {
+       .init_box       = lnl_uncore_sncu_init_box,
+       MMIO_UNCORE_COMMON_OPS()
+};
+
+static struct intel_uncore_type lnl_uncore_sncu = {
+       .name           = "sncu",
+       .num_counters   = 2,
+       .num_boxes      = 1,
+       .perf_ctr_bits  = 64,
+       .perf_ctr       = LNL_UNCORE_SNCU_CTR,
+       .event_ctl      = LNL_UNCORE_SNCU_CTRL,
+       .event_mask     = LNL_UNC_RAW_EVENT_MASK,
+       .box_ctl        = LNL_UNCORE_SNCU_BOX_CTL,
+       .mmio_map_size  = LNL_UNCORE_MAP_SIZE,
+       .ops            = &lnl_uncore_sncu_ops,
+       .format_group   = &lnl_uncore_format_group,
+};
+
+static struct intel_uncore_type *lnl_mmio_uncores[] = {
+       &adl_uncore_imc,
+       &lnl_uncore_hbo,
+       &lnl_uncore_sncu,
+       NULL
+};
+
+void lnl_uncore_mmio_init(void)
+{
+       uncore_mmio_uncores = lnl_mmio_uncores;
+}
+
+/* end of Lunar Lake MMIO uncore support */