[PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356]

It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.

	PR target/120356

gcc/ChangeLog:

	* config/riscv/riscv-v.cc
	(expand_const_vector_interleaved_stepped_npatterns):
	Fix ASHIFT to LSHIFTRT insn.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr120356.c: New test.

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 69f2a1ece534c16d4035d6c5b6529ffecb326a3b..ce1633c72dee7172220f992627d0401f46b7613c 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx target, rtx src,
          shifted_vid = gen_reg_rtx (mode);
          rtx shift = gen_int_mode (1, Xmode);
          rtx shift_ops[] = {shifted_vid, vid, shift};
-         emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+         emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
                           shift_ops);
        }
       else

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
new file mode 100644 (file)
index 0000000..2913f04
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target rvv_zvl256b_ok } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O2" } */
+
+unsigned char a = 5;
+long long c[18];
+
+static void d ()
+{
+  for (short i = 0; i < 60; i += 65413)
+    for (char j = 0; j < 18; j++)
+      {
+       for (char k = 0; k < 18; k++)
+         a *= 143;
+       for (char k = 0; k < 6; k++)
+         for (char l = 0; l < 18; l++)
+           c[l] = 0;
+      }
+}
+
+int main ()
+{
+  d ();
+  if (a + c[0] != 69)
+    __builtin_abort ();
+}