(IMX_PAD_SION | 8) /* SEMC_DQS */
>;
};
+
+ pinctrl_flexspi1: flexspi1grp {
+ fsl,pins = <
+ IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0xa
+ IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0xa
+ IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0xa
+ IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0xa
+ IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0xa
+ IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0xa
+ IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0xa
+ >;
+ };
+ };
+};
+
+&flexspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi1>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <250000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
};
};
#interrupt-cells = <2>;
};
+ flexspi1: spi@400cc000 {
+ compatible = "nxp,imxrt1170-fspi";
+ reg = <0x400cc000 0x800>, <0x30000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <130>;
+ clocks = <&clks IMXRT1170_CLK_DUMMY>,
+ <&clks IMXRT1170_CLK_FLEXSPI1>;
+ clock-names = "fspi_en", "fspi";
+ status = "disabled";
+ };
+
gpt1: gpt1@400ec000 {
compatible = "fsl,imxrt-gpt";
reg = <0x400ec000 0x4000>;
#define IMXRT1170_CLK_GPT1 33
#define IMXRT1170_CLK_SEMC_SEL 34
#define IMXRT1170_CLK_SEMC 35
-#define IMXRT1170_CLK_END 36
+#define IMXRT1170_CLK_FLEXSPI1_SEL 36
+#define IMXRT1170_CLK_FLEXSPI1 37
+#define IMXRT1170_CLK_END 38
#endif /* __DT_BINDINGS_CLOCK_IMXRT1170_H */