The kernel developers have requested such a constraint to use csrxchg
in inline assembly.
gcc/ChangeLog:
* doc/md.texi: Document the 'q' constraint for LoongArch.
A memory operand whose address is formed by a base register and offset
that is suitable for use in instructions with the same addressing mode
as @code{st.w} and @code{ld.w}.
+@item q
+A general-purpose register except for $r0 and $r1 (for the csrxchg
+instruction)
@item I
A signed 12-bit constant (for arithmetic instructions).
@item K