MIPS: lantiq: improve USB initialization

This adds code to initialize the USB controller and PHY also on Danube,
Amazon SE and AR10. This code is based on the Vendor driver from
different UGW versions and compared to the hardware documentation.

This patch is included in OpenWrt for many years.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 3ed0782252229a60d7e72d19b74a0d13e1b04794..5a75283d17f10e94af846c3b7f8e945130a7b8d4 100644 (file)
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -247,6 +247,25 @@ static void pmu_disable(struct clk *clk)
                pr_warn("deactivating PMU module failed!");
 }
 
+static void usb_set_clock(void)
+{
+       unsigned int val = ltq_cgu_r32(ifccr);
+
+       if (of_machine_is_compatible("lantiq,ar10") ||
+           of_machine_is_compatible("lantiq,grx390")) {
+               val &= ~0x03; /* XTAL divided by 3 */
+       } else if (of_machine_is_compatible("lantiq,ar9") ||
+                  of_machine_is_compatible("lantiq,vr9")) {
+               /* TODO: this depends on the XTAL frequency */
+               val |= 0x03; /* XTAL divided by 3 */
+       } else if (of_machine_is_compatible("lantiq,ase")) {
+               val |= 0x20; /* from XTAL */
+       } else if (of_machine_is_compatible("lantiq,danube")) {
+               val |= 0x30; /* 12 MHz, generated from 36 MHz */
+       }
+       ltq_cgu_w32(val, ifccr);
+}
+
 /* the pci enable helper */
 static int pci_enable(struct clk *clk)
 {
@@ -588,4 +607,5 @@ void __init ltq_soc_init(void)
                clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
                clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
        }
+       usb_set_clock();
 }