* 001-RGMII
* 010-SGMII
* 100-RMII
+ * These are the DW MAC phy_intf_sel values
*/
#define MII_PHY_SEL_MASK GENMASK(4, 2)
-#define ETH_PHY_SEL_RMII BIT(4)
-#define ETH_PHY_SEL_SGMII BIT(3)
-#define ETH_PHY_SEL_RGMII BIT(2)
-#define ETH_PHY_SEL_GMII 0x0
-#define ETH_PHY_SEL_MII 0x0
+#define MII_PHY_SEL_VAL(val) FIELD_PREP_CONST(MII_PHY_SEL_MASK, val)
+#define ETH_PHY_SEL_RMII MII_PHY_SEL_VAL(PHY_INTF_SEL_RMII)
+#define ETH_PHY_SEL_SGMII MII_PHY_SEL_VAL(PHY_INTF_SEL_SGMII)
+#define ETH_PHY_SEL_RGMII MII_PHY_SEL_VAL(PHY_INTF_SEL_RGMII)
+#define ETH_PHY_SEL_GMII MII_PHY_SEL_VAL(PHY_INTF_SEL_GMII_MII)
+#define ETH_PHY_SEL_MII MII_PHY_SEL_VAL(PHY_INTF_SEL_GMII_MII)
struct sti_dwmac {
phy_interface_t interface; /* MII interface */