]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/amdgpu/gfx: assign the actual me0 queues per pipe
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 20 Mar 2025 18:24:47 +0000 (14:24 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 7 Apr 2025 19:18:34 +0000 (15:18 -0400)
Set the actual number of queues per pipe for ME0 (gfx).
This way we will dump all of the queues properly in
dev core dumps.

Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

index cba9b973f0a767d5b19c5d7d6cf876ca7887843b..d9c2dab17f6b2514489ef8a2663d16a33ac1f2c5 100644 (file)
@@ -4764,7 +4764,7 @@ static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(10, 1, 4):
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
-               adev->gfx.me.num_queue_per_pipe = 1;
+               adev->gfx.me.num_queue_per_pipe = 8;
                adev->gfx.mec.num_mec = 2;
                adev->gfx.mec.num_pipe_per_mec = 4;
                adev->gfx.mec.num_queue_per_pipe = 8;
@@ -4779,7 +4779,7 @@ static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(10, 3, 7):
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 2;
-               adev->gfx.me.num_queue_per_pipe = 1;
+               adev->gfx.me.num_queue_per_pipe = 2;
                adev->gfx.mec.num_mec = 2;
                adev->gfx.mec.num_pipe_per_mec = 4;
                adev->gfx.mec.num_queue_per_pipe = 4;
index 0c9b28a4605031751820106f3dacf7a1cbb291a0..c78458ecb88b270f54b10035bb06ce8d8297e46c 100644 (file)
@@ -1581,7 +1581,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(11, 0, 3):
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
-               adev->gfx.me.num_queue_per_pipe = 1;
+               adev->gfx.me.num_queue_per_pipe = 2;
                adev->gfx.mec.num_mec = 1;
                adev->gfx.mec.num_pipe_per_mec = 4;
                adev->gfx.mec.num_queue_per_pipe = 4;
@@ -1594,7 +1594,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(11, 5, 3):
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
-               adev->gfx.me.num_queue_per_pipe = 1;
+               adev->gfx.me.num_queue_per_pipe = 2;
                adev->gfx.mec.num_mec = 1;
                adev->gfx.mec.num_pipe_per_mec = 4;
                adev->gfx.mec.num_queue_per_pipe = 4;
index 7b20ab48f762bb1cbd1e6365ece92c0bae2c56b8..ddac26b012bca1a30684a0c3c8cb1589d5984e3c 100644 (file)
@@ -1355,7 +1355,7 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
        case IP_VERSION(12, 0, 1):
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
-               adev->gfx.me.num_queue_per_pipe = 1;
+               adev->gfx.me.num_queue_per_pipe = 8;
                adev->gfx.mec.num_mec = 1;
                adev->gfx.mec.num_pipe_per_mec = 2;
                adev->gfx.mec.num_queue_per_pipe = 4;