riscv/futex: Optimize atomic cmpxchg

Remove redundant release/acquire barriers, optimizing the lr/sc sequence
to provide conditional RCsc synchronization, per the RVWMO.

Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20241113183321.491113-1-dave@stgolabs.net
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/include/asm/futex.h b/arch/riscv/include/asm/futex.h
index fc8130f995c1eea886d4b8d886be42e266f50224..72be100afa236bedb7148247b792626a31b6c35b 100644 (file)
--- a/arch/riscv/include/asm/futex.h
+++ b/arch/riscv/include/asm/futex.h
@@ -85,7 +85,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 
        __enable_user_access();
        __asm__ __volatile__ (
-       "1:     lr.w.aqrl %[v],%[u]                     \n"
+       "1:     lr.w %[v],%[u]                          \n"
        "       bne %[v],%z[ov],3f                      \n"
        "2:     sc.w.aqrl %[t],%z[nv],%[u]              \n"
        "       bnez %[t],1b                            \n"