drm/i915/wcl: C10 phy connected to port A and B

WCL added a c10 phy connected to port B. PTL code is currently
restricting c10 to phy_a only.

PTL doesn't have a PHY connected to PORT B; as such,there will
never be a case where PTL uses PHY B.
WCL uses PORT A and B with the C10 PHY.Reusing the condition
for WCL and extending it for PORT B should not cause any issues
for PTL.

-v2: Reuse and extend PTL condition for WCL (Matt)

Bspec: 73944
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20250613193146.3549862-9-dnyaneshwar.bhadane@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 83c8df9dbc0c0ecd3e006eaf9ad8a9c11bee7602..ed8e640b96b0a1e3d55fbbddfc98c07ab1b67a02 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -39,7 +39,13 @@ bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
        struct intel_display *display = to_intel_display(encoder);
        enum phy phy = intel_encoder_to_phy(encoder);
 
-       if (display->platform.pantherlake && phy == PHY_A)
+       /* PTL doesn't have a PHY connected to PORT B; as such,
+        * there will never be a case where PTL uses PHY B.
+        * WCL uses PORT A and B with the C10 PHY.
+        * Reusing the condition for WCL and extending it for PORT B
+        * should not cause any issues for PTL.
+        */
+       if (display->platform.pantherlake && phy < PHY_C)
                return true;
 
        if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C)