drm/amdgpu: fix MES GFX mask

Current MES GFX mask prevents FW to enable oversubscription. This patch
does the following:
- Fixes the mask values and adds a description for the same
- Removes the central mask setup and makes it IP specific, as it would
  be different when the number of pipes and queues are different.

v2: squash in fix from Shashank

Cc: Christian König <Christian.Koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
Signed-off-by: Arvind Yadav <arvind.yadav@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 85f774063f9b1078af1c51532e7d944cdcde6174..f8202e6ed4b15b98c4f8c952c9fc0955f438592c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -150,9 +150,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
                adev->mes.compute_hqd_mask[i] = 0xc;
        }
 
-       for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++)
-               adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe;
-
        for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
                if (i >= adev->sdma.num_instances)
                        break;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index da2c9a8cb3e011da7b2e22e2146197cfed9a02a9..52dd54a32fb477209550425ec7e5085dc89db96a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -111,8 +111,8 @@ struct amdgpu_mes {
 
        uint32_t                        vmid_mask_gfxhub;
        uint32_t                        vmid_mask_mmhub;
-       uint32_t                        compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
        uint32_t                        gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
+       uint32_t                        compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
        uint32_t                        sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
        uint32_t                        aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
        uint32_t                        sch_ctx_offs[AMDGPU_MAX_MES_PIPES];

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index c34a00500e183dfba5971e3a951cf49281a66179..4cfd86aa2ea3dd49c830523585f8ffdc9d7826a5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -669,6 +669,18 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
                        offsetof(union MESAPI__MISC, api_status));
 }
 
+static void mes_v11_0_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
+{
+       /*
+        * GFX pipe 0 queue 0 is being used by Kernel queue.
+        * Set GFX pipe 0 queue 1 for MES scheduling
+        * mask = 10b
+        * GFX pipe 1 can't be used for MES due to HW limitation.
+        */
+       pkt->gfx_hqd_mask[0] = 0x2;
+       pkt->gfx_hqd_mask[1] = 0;
+}
+
 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
 {
        int i;
@@ -693,8 +705,7 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
                mes_set_hw_res_pkt.compute_hqd_mask[i] =
                        mes->compute_hqd_mask[i];
 
-       for (i = 0; i < MAX_GFX_PIPES; i++)
-               mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
+       mes_v11_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
 
        for (i = 0; i < MAX_SDMA_PIPES; i++)
                mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index e6ab617b9a4041f1766ece1ff58b91a717c772d2..62aba0b5dbe2a298d750596da04e10da4261dd80 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -694,6 +694,17 @@ static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
                        offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
 }
 
+static void mes_v12_0_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
+{
+       /*
+        * GFX V12 has only one GFX pipe, but 8 queues in it.
+        * GFX pipe 0 queue 0 is being used by Kernel queue.
+        * Set GFX pipe 0 queue 1-7 for MES scheduling
+        * mask = 1111 1110b
+        */
+       pkt->gfx_hqd_mask[0] = 0xFE;
+}
+
 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
 {
        int i;
@@ -716,9 +727,7 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
                        mes_set_hw_res_pkt.compute_hqd_mask[i] =
                                mes->compute_hqd_mask[i];
 
-               for (i = 0; i < MAX_GFX_PIPES; i++)
-                       mes_set_hw_res_pkt.gfx_hqd_mask[i] =
-                               mes->gfx_hqd_mask[i];
+               mes_v12_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
 
                for (i = 0; i < MAX_SDMA_PIPES; i++)
                        mes_set_hw_res_pkt.sdma_hqd_mask[i] =