clk: renesas: cpg-mssr: Add du1 clock to R8A7745

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 9e2360a8e14b860ec4a3a5e9982c370b772be178..2859504cc8668199f69f8bd32c4ae3d9c5bdfe3f 100644 (file)
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -129,6 +129,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
        DEF_MOD("scif2",                 719,   R8A7745_CLK_P),
        DEF_MOD("scif1",                 720,   R8A7745_CLK_P),
        DEF_MOD("scif0",                 721,   R8A7745_CLK_P),
+       DEF_MOD("du1",                   723,   R8A7745_CLK_ZX),
        DEF_MOD("du0",                   724,   R8A7745_CLK_ZX),
        DEF_MOD("ipmmu-sgx",             800,   R8A7745_CLK_ZX),
        DEF_MOD("vin1",                  810,   R8A7745_CLK_ZG),