]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
net/mlx5: Switch to more abstract scoped ksimd guard API on arm64
authorArd Biesheuvel <ardb@kernel.org>
Wed, 8 Oct 2025 15:22:36 +0000 (17:22 +0200)
committerArd Biesheuvel <ardb@kernel.org>
Wed, 12 Nov 2025 08:52:02 +0000 (09:52 +0100)
Instead of calling kernel_neon_begin/end directly, switch to the scoped
guard API which encapsulates those calls. This is needed because the
prototypes of those APIs are going to be modified and will require a
kernel mode FP/SIMD buffer to be provided, which the scoped guard API
will do transparently.

Cc: Saeed Mahameed <saeedm@nvidia.com>
Cc: Leon Romanovsky <leon@kernel.org>
Cc: Tariq Toukan <tariqt@nvidia.com>
Cc: Mark Bloch <mbloch@nvidia.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
drivers/net/ethernet/mellanox/mlx5/core/wc.c

index 05e5fd777d4f41bca084f9d3e9c76299dfa0a1be..815a7c97d6b09e06a7caa62f1f041b60d6d0b9e4 100644 (file)
@@ -9,6 +9,7 @@
 
 #if IS_ENABLED(CONFIG_KERNEL_MODE_NEON) && IS_ENABLED(CONFIG_ARM64)
 #include <asm/neon.h>
+#include <asm/simd.h>
 #endif
 
 #define TEST_WC_NUM_WQES 255
@@ -264,15 +265,15 @@ static void mlx5_iowrite64_copy(struct mlx5_wc_sq *sq, __be32 mmio_wqe[16],
 {
 #if IS_ENABLED(CONFIG_KERNEL_MODE_NEON) && IS_ENABLED(CONFIG_ARM64)
        if (cpu_has_neon()) {
-               kernel_neon_begin();
-               asm volatile
-               (".arch_extension simd\n\t"
-               "ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [%0]\n\t"
-               "st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [%1]"
-               :
-               : "r"(mmio_wqe), "r"(sq->bfreg.map + offset)
-               : "memory", "v0", "v1", "v2", "v3");
-               kernel_neon_end();
+               scoped_ksimd() {
+                       asm volatile(
+                               ".arch_extension simd\n\t"
+                               "ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [%0]\n\t"
+                               "st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [%1]"
+                               :
+                               : "r"(mmio_wqe), "r"(sq->bfreg.map + offset)
+                               : "memory", "v0", "v1", "v2", "v3");
+               }
                return;
        }
 #endif