]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
pinctrl: starfive: use dynamic GPIO base allocation
authorAli Tariq <alitariq45892@gmail.com>
Sun, 26 Oct 2025 11:42:40 +0000 (11:42 +0000)
committerLinus Walleij <linusw@kernel.org>
Wed, 3 Dec 2025 23:22:49 +0000 (00:22 +0100)
The JH7110 pinctrl driver currently sets a static GPIO base number from
platform data:

  sfp->gc.base = info->gc_base;

Static base assignment is deprecated and results in the following warning:

  gpio gpiochip0: Static allocation of GPIO base is deprecated,
  use dynamic allocation.

Set `sfp->gc.base = -1` to let the GPIO core dynamically allocate
the base number. This removes the warning and aligns the driver
with current GPIO guidelines.

Since the GPIO base is now allocated dynamically, remove `gc_base` field in
`struct jh7110_pinctrl_soc_info` and the associated `JH7110_SYS_GC_BASE`
and `JH7110_AON_GC_BASE` constants as they are no longer used anywhere
in the driver.

Tested on VisionFive 2 (JH7110 SoC).

Signed-off-by: Ali Tariq <alitariq45892@gmail.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-aon.c
drivers/pinctrl/starfive/pinctrl-starfive-jh7110-sys.c
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
drivers/pinctrl/starfive/pinctrl-starfive-jh7110.h

index cf42e204cbf01bb4cde3c866cfdd8dffb8eed66d..3433b3c916923cd5552e5bae5fca3dacc4e8babb 100644 (file)
@@ -29,7 +29,6 @@
 #include "pinctrl-starfive-jh7110.h"
 
 #define JH7110_AON_NGPIO               4
-#define JH7110_AON_GC_BASE             64
 
 #define JH7110_AON_REGS_NUM            37
 
@@ -138,7 +137,6 @@ static const struct jh7110_pinctrl_soc_info jh7110_aon_pinctrl_info = {
        .pins           = jh7110_aon_pins,
        .npins          = ARRAY_SIZE(jh7110_aon_pins),
        .ngpios         = JH7110_AON_NGPIO,
-       .gc_base        = JH7110_AON_GC_BASE,
        .dout_reg_base  = JH7110_AON_DOUT,
        .dout_mask      = GENMASK(3, 0),
        .doen_reg_base  = JH7110_AON_DOEN,
index 03c2ad808d61c65d3137ef73ad6a208ec8e6ddb7..9b67063a0b0b60c2d57121786bee33742b2b9ef6 100644 (file)
@@ -29,7 +29,6 @@
 #include "pinctrl-starfive-jh7110.h"
 
 #define JH7110_SYS_NGPIO               64
-#define JH7110_SYS_GC_BASE             0
 
 #define JH7110_SYS_REGS_NUM            174
 
@@ -410,7 +409,6 @@ static const struct jh7110_pinctrl_soc_info jh7110_sys_pinctrl_info = {
        .pins           = jh7110_sys_pins,
        .npins          = ARRAY_SIZE(jh7110_sys_pins),
        .ngpios         = JH7110_SYS_NGPIO,
-       .gc_base        = JH7110_SYS_GC_BASE,
        .dout_reg_base  = JH7110_SYS_DOUT,
        .dout_mask      = GENMASK(6, 0),
        .doen_reg_base  = JH7110_SYS_DOEN,
index 05e3af75b09f5b468fca7c2248b6bc79a09bf03b..eb5cf8c067d1e4ab0f145e8bd8aedc7ffe7392cd 100644 (file)
@@ -938,7 +938,7 @@ int jh7110_pinctrl_probe(struct platform_device *pdev)
        sfp->gc.set = jh7110_gpio_set;
        sfp->gc.set_config = jh7110_gpio_set_config;
        sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges;
-       sfp->gc.base = info->gc_base;
+       sfp->gc.base = -1;
        sfp->gc.ngpio = info->ngpios;
 
        jh7110_irq_chip.name = sfp->gc.label;
index a33d0d4e13820d8ca3adfb6316ca496206562827..2da2d6858008ccc2e7b2dd9435062f1a7745b079 100644 (file)
@@ -38,7 +38,6 @@ struct jh7110_pinctrl_soc_info {
        const struct pinctrl_pin_desc *pins;
        unsigned int npins;
        unsigned int ngpios;
-       unsigned int gc_base;
 
        /* gpio dout/doen/din/gpioinput register */
        unsigned int dout_reg_base;