S: Maintained
F: Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml
F: Documentation/driver-api/media/drivers/ccs/
+F: drivers/media/i2c/ccs-pll.c
+F: drivers/media/i2c/ccs-pll.h
F: drivers/media/i2c/ccs/
-F: drivers/media/i2c/smiapp-pll.c
-F: drivers/media/i2c/smiapp-pll.h
F: include/uapi/linux/smiapp.h
MIPS
config VIDEO_APTINA_PLL
tristate
-config VIDEO_SMIAPP_PLL
+config VIDEO_CCS_PLL
tristate
config VIDEO_HI556
obj-$(CONFIG_VIDEO_ADP1653) += adp1653.o
obj-$(CONFIG_VIDEO_LM3560) += lm3560.o
obj-$(CONFIG_VIDEO_LM3646) += lm3646.o
-obj-$(CONFIG_VIDEO_SMIAPP_PLL) += smiapp-pll.o
+obj-$(CONFIG_VIDEO_CCS_PLL) += ccs-pll.o
obj-$(CONFIG_VIDEO_AK881X) += ak881x.o
obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
obj-$(CONFIG_VIDEO_I2C) += video-i2c.o
// SPDX-License-Identifier: GPL-2.0-only
/*
- * drivers/media/i2c/smiapp-pll.c
+ * drivers/media/i2c/ccs-pll.c
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2011--2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
#include <linux/lcm.h>
#include <linux/module.h>
-#include "smiapp-pll.h"
+#include "ccs-pll.h"
/* Return an even number or one. */
static inline uint32_t clk_div_even(uint32_t a)
return -EINVAL;
}
-static void print_pll(struct device *dev, struct smiapp_pll *pll)
+static void print_pll(struct device *dev, struct ccs_pll *pll)
{
dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div);
dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier);
- if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
+ if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) {
dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div);
dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div);
}
dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz);
dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz);
dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz);
- if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
+ if (!(pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)) {
dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n",
pll->op.sys_clk_freq_hz);
dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n",
}
static int check_all_bounds(struct device *dev,
- const struct smiapp_pll_limits *limits,
- const struct smiapp_pll_branch_limits *op_limits,
- struct smiapp_pll *pll,
- struct smiapp_pll_branch *op_pll)
+ const struct ccs_pll_limits *limits,
+ const struct ccs_pll_branch_limits *op_limits,
+ struct ccs_pll *pll, struct ccs_pll_branch *op_pll)
{
int rval;
* If there are no OP clocks, the VT clocks are contained in
* the OP clock struct.
*/
- if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)
+ if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
return rval;
if (!rval)
*
* @return Zero on success, error code on error.
*/
-static int __smiapp_pll_calculate(
- struct device *dev, const struct smiapp_pll_limits *limits,
- const struct smiapp_pll_branch_limits *op_limits,
- struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul,
- uint32_t div, uint32_t lane_op_clock_ratio)
+static int
+__ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
+ const struct ccs_pll_branch_limits *op_limits,
+ struct ccs_pll *pll, struct ccs_pll_branch *op_pll,
+ uint32_t mul, uint32_t div, uint32_t lane_op_clock_ratio)
{
uint32_t sys_div;
uint32_t best_pix_div = INT_MAX >> 1;
op_pll->pix_clk_freq_hz =
op_pll->sys_clk_freq_hz / op_pll->pix_clk_div;
- if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
+ if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
/* No OP clocks --- VT clocks are used instead. */
goto out_skip_vt_calc;
}
return check_all_bounds(dev, limits, op_limits, pll, op_pll);
}
-int smiapp_pll_calculate(struct device *dev,
- const struct smiapp_pll_limits *limits,
- struct smiapp_pll *pll)
+int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
+ struct ccs_pll *pll)
{
- const struct smiapp_pll_branch_limits *op_limits = &limits->op;
- struct smiapp_pll_branch *op_pll = &pll->op;
+ const struct ccs_pll_branch_limits *op_limits = &limits->op;
+ struct ccs_pll_branch *op_pll = &pll->op;
uint16_t min_pre_pll_clk_div;
uint16_t max_pre_pll_clk_div;
uint32_t lane_op_clock_ratio;
unsigned int i;
int rval = -EINVAL;
- if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
+ if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
/*
* If there's no OP PLL at all, use the VT values
* instead. The OP values are ignored for the rest of
op_pll = &pll->vt;
}
- if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
+ if (pll->flags & CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
lane_op_clock_ratio = pll->csi2.lanes;
else
lane_op_clock_ratio = 1;
pll->binning_vertical);
switch (pll->bus_type) {
- case SMIAPP_PLL_BUS_TYPE_CSI2:
+ case CCS_PLL_BUS_TYPE_CSI2:
/* CSI transfers 2 bits per clock per lane; thus times 2 */
pll->pll_op_clk_freq_hz = pll->link_freq * 2
* (pll->csi2.lanes / lane_op_clock_ratio);
break;
- case SMIAPP_PLL_BUS_TYPE_PARALLEL:
+ case CCS_PLL_BUS_TYPE_PARALLEL:
pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
/ DIV_ROUND_UP(pll->bits_per_pixel,
pll->parallel.bus_width);
for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
pll->pre_pll_clk_div <= max_pre_pll_clk_div;
pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
- rval = __smiapp_pll_calculate(dev, limits, op_limits, pll,
- op_pll, mul, div,
- lane_op_clock_ratio);
+ rval = __ccs_pll_calculate(dev, limits, op_limits, pll, op_pll,
+ mul, div, lane_op_clock_ratio);
if (rval)
continue;
return rval;
}
-EXPORT_SYMBOL_GPL(smiapp_pll_calculate);
+EXPORT_SYMBOL_GPL(ccs_pll_calculate);
MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
-MODULE_DESCRIPTION("Generic SMIA/SMIA++ PLL calculator");
+MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ PLL calculator");
MODULE_LICENSE("GPL");
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * drivers/media/i2c/smiapp-pll.h
+ * drivers/media/i2c/ccs-pll.h
*
- * Generic driver for SMIA/SMIA++ compliant camera modules
+ * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
*
+ * Copyright (C) 2020 Intel Corporation
* Copyright (C) 2012 Nokia Corporation
* Contact: Sakari Ailus <sakari.ailus@iki.fi>
*/
-#ifndef SMIAPP_PLL_H
-#define SMIAPP_PLL_H
+#ifndef CCS_PLL_H
+#define CCS_PLL_H
/* CSI-2 or CCP-2 */
-#define SMIAPP_PLL_BUS_TYPE_CSI2 0x00
-#define SMIAPP_PLL_BUS_TYPE_PARALLEL 0x01
+#define CCS_PLL_BUS_TYPE_CSI2 0x00
+#define CCS_PLL_BUS_TYPE_PARALLEL 0x01
/* op pix clock is for all lanes in total normally */
-#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
-#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
+#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
+#define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
-struct smiapp_pll_branch {
+struct ccs_pll_branch {
uint16_t sys_clk_div;
uint16_t pix_clk_div;
uint32_t sys_clk_freq_hz;
uint32_t pix_clk_freq_hz;
};
-struct smiapp_pll {
+struct ccs_pll {
/* input values */
uint8_t bus_type;
union {
uint16_t pll_multiplier;
uint32_t pll_ip_clk_freq_hz;
uint32_t pll_op_clk_freq_hz;
- struct smiapp_pll_branch vt;
- struct smiapp_pll_branch op;
+ struct ccs_pll_branch vt;
+ struct ccs_pll_branch op;
uint32_t pixel_rate_csi;
uint32_t pixel_rate_pixel_array;
};
-struct smiapp_pll_branch_limits {
+struct ccs_pll_branch_limits {
uint16_t min_sys_clk_div;
uint16_t max_sys_clk_div;
uint32_t min_sys_clk_freq_hz;
uint32_t max_pix_clk_freq_hz;
};
-struct smiapp_pll_limits {
+struct ccs_pll_limits {
/* Strict PLL limits */
uint32_t min_ext_clk_freq_hz;
uint32_t max_ext_clk_freq_hz;
uint32_t min_pll_op_freq_hz;
uint32_t max_pll_op_freq_hz;
- struct smiapp_pll_branch_limits vt;
- struct smiapp_pll_branch_limits op;
+ struct ccs_pll_branch_limits vt;
+ struct ccs_pll_branch_limits op;
/* Other relevant limits */
uint32_t min_line_length_pck_bin;
struct device;
-int smiapp_pll_calculate(struct device *dev,
- const struct smiapp_pll_limits *limits,
- struct smiapp_pll *pll);
+int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,
+ struct ccs_pll *pll);
-#endif /* SMIAPP_PLL_H */
+#endif /* CCS_PLL_H */
depends on I2C && VIDEO_V4L2 && HAVE_CLK
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
- select VIDEO_SMIAPP_PLL
+ select VIDEO_CCS_PLL
select V4L2_FWNODE
help
This is a generic driver for MIPI CCS, SMIA++ and SMIA compliant
static int ccs_pll_configure(struct ccs_sensor *sensor)
{
- struct smiapp_pll *pll = &sensor->pll;
+ struct ccs_pll *pll = &sensor->pll;
int rval;
rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt.pix_clk_div);
rval = ccs_write(sensor, REQUESTED_LINK_RATE,
DIV_ROUND_UP(pll->op.sys_clk_freq_hz,
1000000 / 256 / 256));
- if (rval < 0 || sensor->pll.flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)
+ if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
return rval;
rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op.pix_clk_div);
return ccs_write(sensor, OP_SYS_CLK_DIV, pll->op.sys_clk_div);
}
-static int ccs_pll_try(struct ccs_sensor *sensor, struct smiapp_pll *pll)
+static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct smiapp_pll_limits lim = {
+ struct ccs_pll_limits lim = {
.min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
.max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
.min_pll_ip_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ),
.min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK),
};
- return smiapp_pll_calculate(&client->dev, &lim, pll);
+ return ccs_pll_calculate(&client->dev, &lim, pll);
}
static int ccs_pll_update(struct ccs_sensor *sensor)
{
- struct smiapp_pll *pll = &sensor->pll;
+ struct ccs_pll *pll = &sensor->pll;
int rval;
pll->binning_horizontal = sensor->binning_horizontal;
static int ccs_get_mbus_formats(struct ccs_sensor *sensor)
{
struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
- struct smiapp_pll *pll = &sensor->pll;
+ struct ccs_pll *pll = &sensor->pll;
u8 compressed_max_bpp = 0;
unsigned int type, n;
unsigned int i, pixel_order;
!CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
!CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
/* No OP clock branch */
- sensor->pll.flags |= SMIAPP_PLL_FLAG_NO_OP_CLOCKS;
+ sensor->pll.flags |= CCS_PLL_FLAG_NO_OP_CLOCKS;
} else if (CCS_LIM(sensor, SCALING_CAPABILITY)
!= CCS_SCALING_CAPABILITY_NONE ||
CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
/* prepare PLL configuration input values */
- sensor->pll.bus_type = SMIAPP_PLL_BUS_TYPE_CSI2;
+ sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2;
sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
static int jt8ev1_init(struct ccs_sensor *sensor)
{
- sensor->pll.flags |= SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE;
+ sensor->pll.flags |= CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE;
return 0;
}
#include "ccs-quirk.h"
#include "ccs-regs.h"
#include "ccs-reg-access.h"
-#include "../smiapp-pll.h"
+#include "../ccs-pll.h"
#include "smiapp-reg-defs.h"
/*
struct ccs_module_info minfo;
- struct smiapp_pll pll;
+ struct ccs_pll pll;
/* Is a default format supported for a given BPP? */
unsigned long *valid_link_freqs;
projects / thirdparty / kernel / linux.git / commitdiff
